Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal

A lock generator circuit for generating a lock signal indicating whether an output clock signal is locked to an input reference signal, said lock generator circuit comprising:

• a lock detection block generating a lock detection signal indicating whether said output clock signal is locked to said input reference signal;
• an out-of-lock detection block generating an out-of-lock signal indicating whether said output clock signal is out-of-lock with said input reference signal;
• and
• lock generation block receiving said lock detection signal and said out-of-lock detection signal on separate paths, said lock generation block generating said lock signal based on both of said lock detection signal and said out-of-lock detection signal.

A system comprising:

• an application block driven by an output clock signal;
• and
• a signal generation circuit generating said output clock signal synchronized with an input reference signal, said signal generation block comprises:
• a PLL generating said output clock signal;
• and
• a PLL lock generator generating a lock signal representing whether said output clock signal is locked to said input reference signal, wherein said output clock signal is provided to said application block only if said lock signal indicates that said output clock signal is locked to said input reference signal, said PLL lock generator comprising:
• a lock detection block generating a lock detection signal indicating whether said output clock signal is locked to said input reference signal;
• an out-of-lock detection block generating an out-of-lock signal indicating whether said output clock signal is out-of-lock with said input reference signal;
• and
• a lock generation block receiving both said lock detection signal and said out-of-lock detection signal, said lock generation block generating said lock signal based on both of said lock detection signal and said out-of-lock detection signal.

A system comprising:

• an application block driven by an output clock signal;
• and
• a signal generation circuit generating said output clock signal synchronized with an input reference signal, said signal generation block comprises a lock detector block for detecting whether an output clock signal is locked to an input reference signal, said lock detector block comprising:
• a first sampling circuit receiving an up signal as an input and being clocked by a down signal, wherein said up signal indicates that the frequency of said output clock signal is to be increased and said down signal indicates that the frequency of the said output clock signal is to be reduced to lock said output clock signal to said input reference clock signal, said first sampling circuit generating a first output indicating whether said output clock signal is out-of-lock;
• a second sampling circuit receiving said down signal as an input and being clocked by said up signal, said second sampling circuit generating a second output indicating whether said output clock signal is out-of-lock;
• and
• an examining circuit receiving said first output and said second output, and generating a signal indicating that said output clock signal is locked to said input reference signal if both said first output and said second output indicate that said output clock signal is not out-of-lock.

A lock detector block for detecting whether an output clock signal is locked to an input reference signal, said lock detector block comprising:

• means for receiving an up signal and a down signal, wherein said up signal indicates that the frequency of said output clock signal is to be increased and said down signal indicates that the frequency of the said output clock signal is to be reduced to lock said output clock signal to said input reference clock signal;
• means for sampling said up signal clocked by said down signal to generate a first output;
• means for sampling said down signal clocked by said up signal to generate a second output;
• and
• means for examining said first output and said second output to generate a signal indicating that said output clock signal is locked to said input reference signal if both of said first output and said second output indicate that said output clock signal is not out-of-lock.

An out-of-lock detector block for detecting whether an output clock signal is out-of-lock with an input reference signal, said out-of-lock detector block comprising:

• means for receiving an up signal and a down signal,
• wherein said up signal indicates that the frequency of said output clock signal is to be increased and said down signal indicates that the frequency of the said output clock signal is to be reduced to lock said output clock signal to said input reference clock signal;
• and
• means for performing an XOR operation of said up signal and said down signal,
• wherein an output of said XOR gate represents whether said output clock is out-of-lock with said input reference signal.

A lock generator circuit for generating a lock signal indicating whether an output clock signal is locked to an input reference signal, said lock generator circuit comprising:

• means for generating a lock detection signal indicating whether said output clock signal is locked to said input reference signal;
• means for generating an out-of-lock signal indicating whether said output clock signal is out-of-lock with said input reference signal;
• and
• means for generating said lock signal by examining said lock detection signal and said is out-of-lock detection signal.

A method of detecting whether an output clock signal is locked to an input reference signal, said method comprising:

• receiving an up signal and a down signal, wherein said up signal indicates that the frequency of said output clock signal is to be increased and said down signal indicates that the frequency of the said output clock signal is to be reduced to lock said output clock signal to said input reference clock signal;
• sampling said up signal clocked by said down signal to generate a first output;
• sampling said down signal clocked by said up signal to generate a second output;
• and
• examining said first output and said second output to generate a signal indicating that said output clock signal is locked to said input reference signal if both of said first output and said second output indicate that said output clock signal is not out-of-lock.

A method of detecting whether an output clock signal is out-of-lock with an input reference signal, said method comprising:

• receiving an up signal and a down signal,
• wherein said up signal indicates that the frequency of said output clock signal is to be increased and said down signal indicates that the frequency of the said output clock signal is to be reduced to lock said output clock signal to said input reference clock signal;
• and
• performing an XOR operation of said up signal and said down signal,
• wherein an output of said XOR gate represents whether said output clock is out-of-lock with said input reference signal.

A method of generating a lock signal indicating whether an output clock signal is locked to an input reference signal, said method comprising:

• generating a lock detection signal indicating whether said output clock signal is locked to said input reference signal;
• generating an out-of-lock signal indicating whether said output clock signal is out-of-lock with said input reference signal;
• and
• generating said lock signal by examining said lock detection signal and said out-of-lock detection signal.