System and method for matching data and clock signal delays to improve setup and hold times

A method of matching data and clock signal delays within receive logic, comprising the steps of:

• minimizing setup and hold times of said receive logic;
• formulating at least one miniaturized version of a clock buffer located within said receive logic, wherein said at least one miniaturized version of said clock buffer is a scaled version of said clock buffer, said miniaturized version of said clock buffer having a scaling factor of K, said scaling factor representing a number of said miniaturized clock buffers utilized to minimize negative variations experienced by said clock buffer;
• and
• minimizing negative variations experienced by said clock buffer.

A system for matching data and clock signal delays within receive logic, comprising:

• means for minimizing setup and hold times of said receive logic;
• means for formulating at least one miniaturized version of a clock buffer located within said receive logic, wherein said at least one miniaturized version of said clock buffer is a scaled version of said clock buffer, said miniaturized version of said clock buffer having a scaling factor of K, said scaling factor representing a number of said miniaturized clock buffers utilized to minimize negative variations experienced by said clock buffer;
• and
• means for minimizing negative variations experienced by said clock buffer.