Decision directed phase locked loops (DD-PLL) with excess processing power in digital communication systems

9 A decision directed phase locked loop as claimed in claim 1, wherein said phase detector includes a subtractor for subtracting the incoming phase of said baseband complex samples from the current phase estimate to generate said phase differences.

A demodulator for demodulating an input modulated signal in a burst data communications system, comprising:

• a plurality of phase locked loops, each having a first block decoder configured to decode bursts of the input modulated signal at a decode rate to generate a set of associated codewords and a phase/frequency error estimate, wherein one of said plurality of phase locked loops is adapted to selectively apply excess processing power to a burst of said input modulated signal;
• and
• a selection circuit which identifies a burst of said input modulated signal to be demodulated with excess processing power, said selection circuit providing said identified burst to said one of said plurality of phase locked loops which is adapted to selectively apply excess processing power in order to re-process said burst of said input modulated signal.

A communication receiver using a demodulator demodulating an input modulated signal from a transmission channel which is encoded by a sequence of codewords, comprising:

• a plurality of phase locked loops which provide respective estimates of the phase of a burst of said input modulated signal, one of said phase locked loops receiving a burst of the input modulated signal and calculating a phase estimate using a different combination of frequency and initial phase estimate and comprising a first block decoder which decodes the set of vector pairs of the burst of said input modulated signal at a decode rate to generate a set of associated codewords and a phase/frequency error estimate;
• and
• a second block decoder which receives the phase/frequency estimates from said plurality of phase locked loops, wherein one of the bursts is selected based on the decoding of the second block decoder and provided to said one of said plurality of phase locked loops to be re-processed with excess processing power.