Apparatus and method for detecting pilot channel signals with low signal-to-noise
AssigneeSamsung Electronics Co., Ltd.
InventorJoseph Robert Cleveland
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AssigneeSamsung Electronics Co., Ltd.
InventorJoseph Robert Cleveland
Estimating the term…
A CDMA receiver for detecting a pilot channel signal having a known pseudo-random noise (PN) chip sequence, the known PN chip sequence comprising a plurality of known Logic 1 chips and a plurality of known Logic 0 chips. The CDMA receiver comprises: 1) a memory for storing the pilot channel signal as a first original sequence of chip samples; 2) a pseudo-signal generator for re-ordering selected ones of the first original sequence of chip samples to thereby generate a first re-ordered sequence of chip samples, wherein the pseudo-signal generator combines the original sequence of chip samples with the first re-ordered sequence of chip samples to thereby generate a first pseudo-signal sequence of combined chip samples; 3) a first matched filter for computing a first correlation value indicating a relative correlation between the first pseudo-signal sequence of combined chip samples and the known PN chip sequence; and 4) a decision circuit for determining from the first correlation value if the pilot channel signal has been detected.
A CDMA receiver capable of detecting a pilot channel signal having a known pseudo-random noise (PN) chip sequence, said known PN chip sequence comprising a plurality of known Logic 1 chips and a plurality of known Logic 0 chips, said CDMA receiver comprising:
A wireless mobile station capable of communicating with a plurality of base stations in a wireless network, said wireless mobile station comprising a CDMA receiver capable of detecting a pilot channel signal having a known pseudo-random noise (PN) chip sequence, said known PN chip sequence comprising a plurality of known Logic 1 chips and a plurality of known Logic 0 chips, said CDMA receiver comprising:
A method of detecting a pilot channel signal having a known pseudo-random noise (PN) chip sequence, the known PN chip sequence comprising a plurality of known Logic 1 chips and a plurality of known Logic 0 chips, the method comprising the steps of:
Dependencies are inferred from the claim text.