Semiconductor device having phase error improved DLL circuit mounted thereon
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYasuhiro Kashiwazaki
Life of this patent
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Abstract
Two delay lines included in a DLL circuit receive clock signals complementary to each other to output complementary clock signals CLKP and CLKN for data output. A power supply generation circuit applying a power supply to the two delay lines is arranged at an equivalent position from the two delay line. An equal potential is supplied to the two delay lines by, for example, setting lengths of two power supply lines from a branch point equal to each other. By doing so, delay time of one delay line can be set equal to delay time of the other delay line and a phase error between clock signals CLKP and CLKN can be reduced. Therefore, a semiconductor device on which the DLL circuit having the improved phase error is mounted can be provided.
Claims16
A semiconductor device comprising:
- a delay locked loop circuit generating first and second internal clock signals in accordance with first and second external clock signals complementary to each other and applied from an outside, said delay locked loop circuit including
- a first variable delay circuit delaying said first external clock signal to output said first internal clock signal,
- a second variable delay circuit delaying said second external clock signal to output said second internal clock signal,
- a delay circuit receiving and delaying said first internal clock signal, and
- a phase comparison circuit comparing a phase of an output of said delay circuit with a phase of said first external clock signal to output a control signal according to a phase difference to said first and second variable delay circuits;
- and
- a potential supply section connected to said first variable delay circuit and connected to said second variable delay circuit in an electrically equivalent connection relationship to connection to said first variable delay circuit, and supplying a power supply potential to said first and second variable delay circuits.
A semiconductor device comprising:
- a delay locked loop circuit generating first and second internal clock signals in accordance with first and second external clock signals complementary to each other and applied from an outside, said delay locked loop circuit including
- a first variable delay circuit delaying said first external clock signal to output said first internal clock signal,
- a second variable delay circuit delaying said second external clock signal to output said second internal clock signal,
- a delay circuit receiving and delaying said first internal clock signal, and
- a phase comparison circuit comparing a phase of an output of said delay circuit with a phase of said first external clock signal, and outputting a control signal according to a phase difference to said first and second variable delay circuits;
- an output buffer circuit outputting data to the outside in accordance with said first and second internal clock signals;
- and
- first and second clock signal lines transmitting said first and second internal clock signals to said output buffer, respectively, wherein
- a resistance value of said first clock signal line is substantially equal to a resistance value of said second clock signal line.
A semiconductor device comprising:
- a delay locked loop circuit generating first and second internal clock signals complementary to each other in accordance with an external clock signal applied from an outside, said delay locked loop circuit including
- a variable delay circuit outputting a third internal clock signal in accordance with said external clock signal;
- a phase adjustment circuit outputting said first internal clock signal in accordance with said third internal clock signal, and outputting said second internal clock signal having a falling edge equal in phase to a rising edge of said first internal clock signal and having a rising edge equal in phase to a falling edge of said first internal clock signal;
- a delay circuit receiving and delaying said first internal clock signal;
- and
- a phase comparison circuit comparing a phase of an output of said delay circuit with a phase of said external clock signal, and outputting a control signal according to a phase difference to said variable delay circuit.
Dependencies are inferred from the claim text.