DRAM with segmental cell arrays and method of accessing same

A semiconductor memory device comprising:

• A plurality of memory blocks accessible by a common row address and a block row address;
• a bit line and a sense amplifier corresponding to each memory cell in each memory block, each sense amplifier for sensing data to be read from the corresponding memory cell;
• a hidden precharge control circuit for inhibiting the activation of a precharge signal at the end of a first memory access operation when successive memory access operations are to be performed with the first memory access operation at a first row address and a first memory block and the next memory access operation at the same first row address and a second memory block having a block address different from the first memory block.

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory blocks having respective block word lines and sharing a global word line;
• and
• a block address generator responsive to a GAPLESS OPERATION CONTROL signal having a first state for signaling a gapless successive read operation to generate a block address having the same global word line to activate each of the plurality of memory blocks according to the block address, wherein each of said memory blocks activated is accessible until a precharge command is issued.