Apparatus and method for parallel programming of antifuses
AssigneeMicron Technology, Inc.
InventorsScott N. Gatzemeier, Wallace E. Fister
Life of this patent
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Abstract
A method and apparatus for programming programmable elements of a plurality of memory devices in parallel. Each of the memory devices include an address latch for latching an address corresponding to a programmable element to be programmed and logic circuitry for receiving address load commands. The logic circuitry provides control signals to the address latch in response to receiving the load commands to cause the address latch to latch an corresponding to a programmable element to be programmed. By using the address latch and logic circuitry, the programming of a programmable element of a first memory device and the programming the second programmable element of a second memory device can occur in parallel.
Claims35
A method for programming programmable elements of a plurality of memory devices, each memory device having at least a first and second programmable element thereon, the method comprising:
- programming the first programmable element of a first memory device of the plurality;
- and
- programming the second programmable element of a second memory device of the plurality, the programming of the first and second programmable elements overlapping at least for a period of time.
The method for programming programmable elements of a plurality of memory devices, comprising:
- in a first memory device of the plurality, latching a first address corresponding to a programmable element located at a first location on the memory devices;
- initiating a programming event to program the programmable element in the first memory device located at the first location;
- in a second memory device of the plurality, latching a second address corresponding to a programmable element located at a second location on the memory devices;
- and
- before the completion of the programming event for the programmable element in the first memory device, initiating a programming event to program the programmable element in the second memory device located at the second location.
A method for an external tester to program programmable elements of a plurality of memory devices, comprising:
- commanding a first of the memory devices to latch a first address corresponding to a programmable element located at a first location on the memory devices;
- commanding a second of the memory devices to latch a second address corresponding to a programmable element located at a second location on the memory devices;
- and
- programming the programmable elements of the first and second of the memory devices substantially concurrently.
A method for an external tester to program antifuses of a plurality of memory devices, comprising:
- providing to a first memory device of the plurality an address corresponding to a programmable element to be programmed in the first memory device;
- providing a load command to the first memory device to latch the address;
- providing to a second memory device of the plurality an address corresponding to a programmable element t to be programmed in the second memory device;
- and
- providing a load command to the second memory device to latch the address .
A memory device having external address terminals and an array of memory with redundant memory to replace memory cells therein in accordance with programmed programmable elements, the memory device comprising:
- an address latch for latching an address corresponding to a programmable element to be programmed by a programming event;
- logic circuitry coupled to the address latch, the logic circuitry receiving address load commands and providing control signals to the address latch in response thereto to cause the address latch to latch an address applied to the external address terminals as the address corresponding to a programmable element to be programmed;
- and
- programming circuitry coupled to the address latch and at least a portion of the programmable elements, the programming circuitry performing a programming event to program the programmable element corresponding to the latched address.
A memory device having external address terminals and an array of memory with redundant memory to replace memory cells therein in accordance with programmed antifuses, the memory device comprising:
- a bank address latch for latching a bank address corresponding to an antifuse bank in which an antifuse to be programmed by a programming event is located;
- a fuse address latch for latching an antifuse address corresponding to the antifuse to be programmed by the programming event;
- and
- logic circuitry coupled to the bank and fuse address latches, the logic circuitry receiving address load commands and providing control signals to the bank and fuse address latches in response thereto to cause the latches to latch the respective addresses applied to the external address terminals as the address corresponding to the programmable element to be programmed.
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising:
- external address terminals;
- an array of memory with redundant memory to replace memory cells therein in accordance with programmed programmable elements;
- an address latch for latching an address corresponding to a programmable element to be programmed by a programming event;
- logic circuitry coupled to the address latch, the logic circuitry receiving address load commands and providing control signals to the address latch in response thereto to cause the address latch to latch an address applied to the external address terminals as the address corresponding to a programmable element to be programmed;
- and
- programming circuitry coupled to the address latch and at least a portion of the programmable elements, the programming circuitry performing a programming event to program the programmable element corresponding to the latched address.
Dependencies are inferred from the claim text.