Dynamic semiconductor memory device and method of controlling refresh thereof

A dynamic semiconductor memory device including a memory cell array having a plurality of memory cells arranged in an array form, having a hierarchical word line structure in which one main word line comprises a plurality of sub-word lines, said dynamic semiconductor memory device comprising:

• a latch circuit for holding a write history associated with each of plurality of units, each of said units partitioned by said main word line, a plurality of said memory cells connected to respective ones of said plurality of sub-word lines associated with said main word line composing said unit;
• and
• a control circuit for controlling activation and inactivation of a selected sub-word line, based on the write history information latched by said latch circuit, when a refresh command for memory cells in one of said units is issued, thereby controlling whether to execute a refresh operation or not.

A dynamic semiconductor memory device including a memory cell array with a plurality of memory cells arranged in an array form, having a hierarchical word line structure in which one main word comprises a plurality of sub-word lines, the dynamic semiconductor memory device comprising:

• a latch circuit for holding a write history associated with each of a plurality of units, each of said units partitioned by said main word line, a plurality of said memory cells connected to respective ones of said plurality of sub-word lines associated with said main word line composing said unit;
• and
• a control circuit for controlling activation and inactivation of a signal for controlling sensing operation by a sense amplifier associated with said latch circuit, based on the write history information latched by said latch circuit, when a refresh command for memory cells in one of said units is issued, thereby controlling whether to execute a refresh operation or not.

A method of controlling refresh operation on a dynamic semiconductor memory device, said method comprising the steps of:

• storing and holding a value representative of presence of a write history in a latch circuit when a word line supplied from a row decoder to a memory cell array and a write command signal for commanding write operation are activated;
• exercising control so that, when said word line and said refresh command signal for commanding a refresh operation on said word line are activated, a refresh operation is performed in case an output of said latch circuit indicates the value representative of the presence of the write history,
• while activation of a selected word line is stopped and/or stopping at least part of a sensing operation by a sense amplifier is stopped, in case the output of said latch circuit indicates a value representative of absence of the write history, thereby reducing refresh current in comparison with refresh current consumed by said normal refresh operation.

A method of controlling refresh operation on a dynamic semiconductor memory device, said method comprising the steps of:

• storing and holding a value representative of presence of a write history in a latch circuit when a word line supplied from a row decoder to a memory cell array and a write command signal for commanding write operation are activated;
• exercising control so that, when said word line and a refresh command signal for commanding a refresh operation on said word line are activated, a normal refresh operation is performed, in case an output of said latch circuit indicates the value representative of the presence of the write history and
• exercising control so that, when said word line and said refresh command signal for commanding a refresh operation on said word line are activated, at least one of control signals for controlling a sensing operation by a sense amplifier is inactivated to stop the refresh operation on said word line, thereby reducing refresh current in comparison with refresh current consumed by said normal refresh operation, in case the output of said latch circuit indicates a value representative of absence of the write history.