System and method for providing asynchronous SRAM functionality with a DRAM array
AssigneeSilicon Storage Technology, Inc.
InventorRobin Tang
Life of this patent
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Abstract
A system 100 which provides asynchronous SRAM functionality with a DRAM device. The system 100 includes an address transition detector circuit 102, a memory clock generator circuit 104, a refresh timer 106, a refresh address counter 108, a memory access controller 110, a memory control sequencer 112, an address buffer 114, a write data buffer 116, a three-input address multiplexer 118, a two-input data multiplexer 120, inverters 122, 124, 126, and 128, AND gates 130, 132, and 134, NOR gates 136, 138, 140, and 142, OR gate 156, and a DRAM array 144 of memory cells. The components of system 100 cooperate to selectively interrupt external memory commands, such as read and write commands, in order to perform refresh operations on array 144.
Claims20
1) A memory system having asynchronous SRAM functionality comprising:
- a DRAM array;
- a first portion adapted to receive external memory commands and to detect external address transitions in order to perform read and write operations on said DRAM array asynchronously;
- and
- a second portion adapted to selectively interrupt said external memory commands in order to perform refresh operations on said DRAM array.
7) A DRAM apparatus having asynchronous SRAM functionality comprising:
- a DRAM array;
- a first portion which is adapted to receive external memory commands, including external memory addresses for performing read and write operations on said DRAM array asynchronously;
- a second portion which is adapted to periodically generate interrupt signals for refreshing said DRAM array;
- a third portion which is adapted to receive data for write operations on said array;
- and
- a fourth portion which is adapted to control said read and write operations performed on said DRAM array, and to interrupt said external memory commands to perform refresh operations said DRAM memory array in response to said generated interrupt signals.
15) A method for providing asynchronous SRAM functionality with a DRAM array, comprising the steps of:
- receiving external memory commands;
- detecting an external address transition in order to perform read and write operations on said DRAM array asynchronously;
- and
- selectively interrupting said external memory commands to perform internal refresh operations on said DRAM array.
Dependencies are inferred from the claim text.