FIFO memory devices having single data rate (SDR) and dual data rate (DDR) capability

A first-in first-out (FIFO) memory device, comprising:

• a plurality of memory devices;
• and
• an input multiplexer that provides said plurality of memory devices with write data in-sync with rising and falling edges of a write clock signal when the FIFO memory device is disposed in a dual data rate (DDR) write mode.

A first-in first-out (FIFO) memory device, comprising:

• a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal and DDR or SDR read modes that operate in-sync with a read clock signal;
• and
• flag circuitry that evaluates an empty condition in the FIFO memory device by comparing a write counter value that is generated off a trailing edge of the write clock signal against a read counter value that is generated off a leading edge of the read clock signal when the FIFO memory device is disposed in the DDR write mode.

A first-in first-out (FIFO) memory device, comprising:

• a plurality of multi-port cache memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal and DDR or SDR read modes that operate in-sync with a read clock signal.

A first-in first-out (FIFO) memory device, comprising:

• a plurality of memory devices that are configured to support a dual data rate (DDR) read mode that operates in-sync with leading and trailing edges of a read clock signal;
• and
• read control circuitry that marks, in response to an active mark signal, data read from the FIFO memory device in response to a trailing edge of a first cycle of the read clock signal during the DDR read mode and retransmits, in response to an active retransmit signal, a stream of read data that commences with data previously read from the FIFO memory device in response to a leading edge of the first cycle of the read clock signal and then follows with the marked read data.

A first-in first-out (FIFO) memory device, comprising:

• a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal and DDR or SDR read modes that operate in-sync with a read clock signal;
• and
• flag circuitry that evaluates a full condition in the FIFO memory device by comparing a marked read counter value, which is generated off a trailing edge of a cycle of the read clock signal that follows closest in time a leading edge of an active mark signal, against a write counter value that is generated off a leading edge of the write clock signal when the FIFO memory device is disposed in the DDR read mode.

A first-in first-out (FIFO) memory device, comprising:

• first, second, third and fourth quad-port cache memory devices that are configured in a quad arrangement to support both dual data rate (DDR) and single data rate (SDR) write modes.