Dynamic RAM and semiconductor device

A dynamic RAM, comprising:

• first and second memory mats respectively comprising a plurality of dynamic memory cells each comprising a MOSFET and a capacitor, said MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, and a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells;
• a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs of the first and second memory mats placed so as to extend in directions opposite to each other from each pair of input/output terminals;
• first electrodes provided so as to correspond to the storage nodes of capacitors in the first memory array;
• second electrodes provided so as to correspond to the storage nodes of capacitors in the second memory array;
• and
• connecting portions which are formed of the same material as the first and second electrodes and interconnect the first and second electrodes with the sense amplifier array interposed therebetween.

A dynamic RAM, comprising:

• first and second memory mats respectively comprising a plurality of dynamic memory cells each comprising a MOSFET and a capacitor, said MOSFET having a gate set as a select terminal, one of source and drain set as input/output terminals, and the other of source and drain connected to storage nodes of the capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, and a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells;
• a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs of the first and second memory mats placed so as to extend in directions opposite to each other from each pair of input/output terminals;
• first electrodes provided so as to correspond to the storage nodes of capacitors in the first memory array;
• second electrodes provided so as to correspond to the storage nodes of capacitors in the second memory array;
• and
• connecting portions which are formed in the same process step as the first and second electrodes and interconnect the first and second electrodes with the sense amplifier array interposed therebetween.

A dynamic RAM, comprising:

• first and second memory mats respectively comprising a plurality of dynamic memory cells each comprising a MOSFET and a capacitor, said MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, and a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells;
• a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs of the first and second memory mats placed so as to extend in directions opposite to each other from each pair of input/output terminals;
• first electrodes provided so as to correspond to the storage nodes of capacitors in the first memory mat;
• second electrodes provided so as to correspond to the storage nodes of capacitors in the second memory mat;
• and
• connecting portions which are formed in the same layer as the first and second electrodes and interconnect the first and second electrodes with the sense amplifier array interposed therebetween.

A dynamic RAM, comprising:

• a plurality of dynamic memory cells each comprising a MOSFET and a capacitor, said MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor;
• a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells;
• a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells;
• and
• a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals;
• and
• wherein power supply lines are provided in mesh form inclusive of a portion above a memory array in which the dynamic memory cells are formed.

A semiconductor device, comprising:

• a first memory mat including a plurality of first bit lines, a plurality of first word lines, and a plurality of first memory cells respectively connected to the plurality of first bit lines and the plurality of first word lines;
• a second memory mat including a plurality of second. bit lines, a plurality of second word lines, and a plurality of second memory cells respectively connected to points where the plurality of second bit lines and the plurality of second word lines intersect;
• and
• a plurality of sense amplifiers formed in a region between said first memory mat and said second memory mat;
• and
• wherein each of said plurality of sense amplifiers is connected to a corresponding one of the plurality of first bit lines and a corresponding one of the plurality of second bit lines,
• each of the plurality of first memory cells includes a first capacitor having first and second electrodes, and a first transistor having a gate coupled to a corresponding one of the plurality of first word lines and a source to drain path whose one is coupled to the corresponding one of the plurality of first bit lines and whose other is connected to the first electrode of the first capacitor,
• each of the plurality of second memory cells includes a second capacitor having third and fourth electrodes, and a second transistor having a gate coupled to a corresponding one of the plurality of second word lines and a source to drain path whose one is coupled to a corresponding one of the plurality of second bit lines and whose other is coupled to the fourth electrode of the second capacitor, and
• the second electrodes of the first capacitors of the plurality of first memory cells, and the fourth electrodes of the second capacitors of the plurality of second memory cells are respectively coupled to one conductive layer placed on the first memory mat, the second memory mat and the plurality of sense amplifiers.

A semiconductor device, comprising:

• a first memory mat including a plurality of first bit lines, a plurality of first word lines, and a plurality of first memory cells respectively connected to the plurality of first bit lines and the plurality of first word lines;
• a second memory mat including a plurality of second bit lines, a plurality of second word lines, and a plurality of second memory cells respectively connected to points where the plurality of second bit lines and the plurality of second word lines intersect;
• and
• a plurality of sense amplifiers formed in a region between said first memory mat and said second memory mat;
• and
• wherein each of said plurality of sense amplifiers is connected to a corresponding one of the plurality of first bit lines and a corresponding one of the plurality of second bit lines,
• each of the plurality of first memory cells includes a first capacitor having first and second electrodes, and a first transistor having a gate coupled to a corresponding one of the plurality of first word lines and a source to drain path whose one is coupled to the corresponding one of the plurality of first bit lines and whose other is connected to the first electrode of the first capacitor,
• each of the plurality of second memory cells includes a second capacitor having third and fourth electrodes, and a second transistor having a gate coupled to a corresponding one of the plurality of second word lines and a source to drain path whose one is coupled to a corresponding one of the plurality of second bit lines and whose other is coupled to the fourth electrode of the second capacitor,
• the second electrodes of the first capacitors of the plurality of first memory cells are respectively coupled to a first conductive layer placed on the plurality of first memory cells,
• the fourth electrodes of the second capacitors of the plurality of second memory cells are respectively coupled to a second conductive layer placed on the plurality of second memory cells, and
• the first conductive layer and the second conductive layer are coupled to each other by connecting portions formed of the same material as the first conducive layer and the second conductive layer and placed on the plurality of sense amplifiers.

A semiconductor device, comprising:

• a first memory mat including a plurality of first bit lines, a plurality of first word lines, and a plurality of first memory cells respectively connected to the plurality of first bit lines and the plurality of first word lines;
• a second memory mat including a plurality of second bit lines, a plurality of second word lines, and a plurality of second memory cells respectively connected to points where the plurality of second bit lines and the plurality of second word lines intersect;
• and
• a plurality of sense amplifiers formed in a region between said first memory mat and said second memory mat;
• wherein each of said plurality of sense amplifiers is connected to a corresponding one of the plurality of first bit lines and a corresponding one of the plurality of second bit lines,
• each of the plurality of first memory cells includes a first capacitor having first and second electrodes, and a first transistor having a gate coupled to a corresponding one of the plurality of first word lines and a source to drain path whose one is coupled to the corresponding one of the plurality of first bit lines and whose other is connected to the first electrode of the first capacitor, and
• each of the plurality of second memory cells includes a second capacitor having third and fourth electrodes, and a second transistor having a gate coupled to a corresponding one of the plurality of second word lines and a source to drain path whose one is coupled to a corresponding one of the plurality of second bit lines and whose other is coupled to the fourth electrode of the second capacitor;
• a plurality of first voltage wires which are formed in a first layer on the first memory mat, the second memory mat and the sense amplifiers and extend in a first direction;
• and
• a plurality of second voltage wires which are formed in a second layer on the first layer, extend in a second direction different from the first direction, and are respectively coupled to the plurality of first voltage wires by a portion for connecting between the first layer and the second layer.