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US 2003/0112681 A1Published application
Fast-sensing amplifier for flash memory
AssigneeMicron Technology, Inc.
InventorMichael S. Briner
Life of this patent
Estimating the term…
Abstract
A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.
Claims65
A read-biasing circuit for sensing the binary state of a floating-gate memory device and having an input line and an output line, comprising:
- a quick-charging circuit operatively coupled to the input line and the output line which quickly raises the potential of the input line to a predetermined first voltage if the device is in one binary state and to a predetermined second voltage if the device is in its other binary state and the potential of the output line to a predetermined third voltage if the device is in one binary state and to a predetermined fourth voltage if the device is in its other binary state;
- and
- a feedback circuit operatively coupled to the input line which prevents the potential of the input line from considerably exceeding a predetermined overshoot voltage.
A high-speed sensor for sensing the binary state of a floating-gate memory device, comprising:
- a differential amplifying circuit having a first input line, a second input line, and an output line which amplifies the difference between a potential at the first input line and a potential at the second input line;
- a memory array which stores a plurality of binary states and having a column line;
- a quick-discharge circuit operatively coupled to the column line of said memory array which quickly discharges the column line to a predetermined voltage;
- a read-biasing circuit having an input line and an output line, the output line operatively coupled to the first input line of said differential amplifying circuit and the input line operatively coupled to the column line of said memory array which quickly senses the potential at the column line after discharge;
- and
- a sense-reference circuit operatively coupled to the second input line of said differential amplifying circuit which provides a predetermined sense-reference potential.
3 more elements
A method for sensing the binary state of a floating-gate memory device, comprising the steps of:
- discharging the device to a predetermined voltage;
- sensing the potential at the device after discharge;
- amplifying the sensed potential at the device;
- comparing the sensed potential at the device with an amplified predetermined sense-reference potential;
- and
- amplifying the difference between the sensed potential at the device and the amplified predetermined sense-reference potential.
3 more elements
A computer, comprising:
- a microprocessor;
- a timing unit;
- an I/O interface module;
- a volatile memory array;
- a non-volatile memory array comprised of a plurality of selectively ordered floating gate memory devices and having an input line and an output line;
- a quick-charging circuit operatively coupled to the input line and the output line which quickly raises the potential of the input line to a predetermined first voltage if the device is in one binary state and to a predetermined second voltage if the device is in its other binary state and the potential of the output line to a predetermined third voltage if the device is in one binary state and to a predetermined fourth voltage if the device is in its other binary state;
- and
- a feedback circuit operatively coupled to the input line which prevents the potential of the input line from considerably exceeding a predetermined overshoot voltage.
5 more elements
A read-biasing and amplifying circuit, comprising:
- an input;
- an output;
- a first load having a node;
- a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load;
- a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output;
- a second load having a node, wherein the node of the second load is coupled to the output;
- a third control device having a signal input, wherein the signal input of the third control device is coupled to the output;
- wherein the second load comprises a fourth control device;
- wherein the node of the second load is a signal input of the fourth control device;
- and
- wherein the first load is a fifth control device, a control input of the fourth control device is coupled to a control input of the fifth control device, and a control input of the third control device is coupled to the output.
8 more elements
A read-biasing and amplifying circuit, comprising:
- an input;
- an output;
- a first load having a node;
- a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load;
- a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output;
- a second load having a node, wherein the node of the second load is coupled to the output;
- a third control device having a signal input, wherein the signal input of the third control device is coupled to the output;
- a fourth control device including a control input and a controlled signal output;
- wherein the second load comprises a fifth control device;
- wherein the node of the second load is a signal input of the fifth control device;
- and
- wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to the output, and a the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
9 more elements
A read-biasing and amplifying circuit, comprising:
- an input;
- an output;
- a first load having a node;
- a first control device having a control input and a controlled signal output, wherein the control input of the first control device is coupled to the input, and the controlled signal output of the first control device is coupled to the node of the first load;
- a second control device having a control input, a controlled signal output, and a signal input, wherein the control input of the second control device is coupled to the controlled signal output of the first control device, the signal input of the second control device is coupled to the input, and the controlled signal output of the second control device is coupled to the output;
- a second load having a node, wherein the node of the second load is coupled to the output;
- a third control device having a signal input, wherein the signal input of the third control device is coupled to the output;
- a fourth control device including a control input and a controlled signal output;
- wherein the second load comprises a fifth control device;
- wherein the node of the second load is a signal input of the fifth control device;
- and
- wherein the first load is a sixth control device, the control input of the fourth control device is coupled to a control input of the sixth control device, a control input of the third control device is coupled to a controlled signal output of the third control device, and the controlled signal output of the fourth control device is coupled to the controlled signal output of the first control device.
9 more elements
A circuit, including:
- an input;
- an output;
- quick-charging means for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised;
- a load for a memory device being sensed, and
- a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
2 more elements
A circuit, including:
- an input;
- an output;
- quick-charging means for simultaneously raising potentials of a bit line and the output;
- a load for a memory device being sensed, and
- a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
2 more elements
A circuit, comprising:
- an input;
- an output;
- a first transistor including a source and a well both connected to a first voltage, the first transistor including a gate and a drain;
- a second transistor including a source and a well both connected to the first voltage, the second transistor including a gate and a drain, wherein the second transistor gate is connected to the first transistor gate and a second voltage;
- a third transistor including a source and a well both connected to the first voltage, the third transistor including a gate and a drain both connected to the output;
- a fourth transistor including a source connected to the second voltage, a gate connected to the input, and a drain connected the first transistor drain;
- and
- a fifth transistor including a source connected to the input, a gate connected to the fourth transistor drain, and a drain connected to the output.
5 more elements
A circuit, comprising:
- an input;
- an output;
- a first transistor including a source and a well both connected to a first voltage, the first transistor including a gate and a drain;
- a second transistor including a source and a well both connected to the first voltage, the second transistor including a gate and a drain, wherein the second transistor gate is connected to the first transistor gate and a second voltage;
- and
- a feedback biasing circuit, wherein the feedback biasing circuit consists of:
- a third transistor including a source and a well both connected to the first voltage, the third transistor including a gate and a drain both connected to the output;
- a fourth transistor including a source connected to the second voltage, a gate connected to the input, and a drain connected the first transistor drain;
- and
- a fifth transistor including a source connected to the input, a gate connected to the fourth transistor drain, and a drain connected to the output.
7 more elements
A read-biasing and amplifying system, comprising:
- a first read-biasing and amplifying circuit;
- a second read-biasing and amplifying circuit;
- and
- a differential amplifier connected between the first circuit and the second circuit.
1 more element
A circuit, including:
- a bit line input;
- an output;
- quick-charging means for raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised;
- a load for a memory device being sensed, and
- a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
2 more elements
A circuit, including:
- an input;
- an output;
- quick-charging means, operatively coupled to the input and the output, for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised;
- a resistive load for a memory device being sensed, wherein the load is distinct from the quick-charging means;
- and
- a feedback means for preventing the potential of the bit line from exceeding a read-bias potential.
3 more elements
A circuit, including:
- an input adapted to be operatively coupled to the bit line;
- an output adapted to be operatively coupled to a microprocessor;
- quick-charging means, operatively coupled to the input and the output, for simultaneously raising potentials of a bit line and the output and for continuing to raise the potential of the output when the potential of the bit line is no longer raised;
- a resistive load for a memory device being sensed, wherein the load is distinct from the quick-charging means;
- and
- a feedback means, operatively coupled to the input, for preventing the potential of the bit line from exceeding a read-bias potential, wherein the feedback means includes a p-channel MOSFET operatively coupled to a first n-channel MOSFET, and a second n-channel MOSFET operatively coupled to the first n-channel MOSFET.
3 more elements
Dependencies are inferred from the claim text.