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US 2003/0112680 A1Published application
Integrated memory having a precharge circuit for precharging a bit line
AssigneeInfineon Technologies AG
InventorThomas Nirschl
Life of this patent
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Abstract
An integrated memory having a memory cell array: including word lines for selecting memory cells, bit lines for reading out or writing data signals of the memory cells, a precharge circuit for precharging at least one of the bit lines to a precharge voltage that differs from a supply voltage of the memory. The precharge circuit has a loop regulating circuit for setting the precharge voltage using an actual voltage of the one of the bit lines. The precharge circuit makes it possible to reduce the power loss of the memory in conjunction with low area consumption.
Claims6
An integrated memory, comprising:
- a memory cell array including a plurality of memory cells, a plurality of word lines for selecting said plurality of said memory cells and a plurality of bit lines for reading out or writing data signals of said plurality of said memory cells;
- and
- a precharge circuit connected to at least one of said plurality of said bit lines, said precharge circuit for precharging said one of said plurality of said bit lines to a precharge voltage generated from a supply voltage being different from said precharge voltage;
- said precharge circuit having a loop regulating circuit for setting said precharge voltage using an actual voltage of said one of said plurality bit lines.
1 more element
Dependencies are inferred from the claim text.