US 2003/0112679 A1 · Semiconductor memory device having mesh-type structure of precharge voltage line

Abstract

A semiconductor memory device having a mesh-type structure of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays. During a first mode of operation, the firs precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second precharge voltage line, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.

Claims22

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cell arrays arranged in a matrix, each of the plurality of memory cell arrays having a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells;
a plurality of bit line precharge circuit units for precharging and equalizing corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages;
and
a first precharge voltage line and a second precharge voltage line arranged in each region between the plurality of memory cell arrays,
wherein during a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second mode of operation, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.

2 more elements

A semiconductor memory device comprising:

a plurality of memory cell arrays arranged in a matrix, each of the plurality of memory cell arrays having a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells;
a plurality of bit line precharge circuit units for precharging and equalizing corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages;
first and second row precharge voltage lines arranged alternately in a first predetermined direction, the first row precharge voltage line for supplying a first precharge voltage to first bit line precharge circuit units and the second row precharge voltage line for supplying a second precharge voltage to second bit line precharge circuit units;
and
first and second column precharge voltage lines arranged alternately in a second predetermined direction, the first column precharge voltage line for supplying the first precharge voltage to the first bit line precharge circuit units and the second column precharge voltage line for supplying the second precharge voltage to the second bit line precharge circuit units,
wherein the first and second precharge voltages are different voltage levels in a predetermined test mode and are the same voltage level in a normal operation mode.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having mesh-type structure of precharge voltage line

Life of this patent

Semiconductor memory device having mesh-type structure of precharge voltage line

Life of this patent

Abstract

Claims22