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US 2003/0112678 A1Published application
Register files and caches with digital sub-threshold leakage current calibration
AssigneeIntel Corporation
InventorsSteven K. Hsu, Shih-Lien L. Lu, Ram Krishnamurthy
Life of this patent
Estimating the term…
Abstract
A memory circuit, such as a cache or register file, where the keeper functional units are digitally controlled to compensate for variable sub-threshold leakage current.
Claims15
A memory device comprising:
- a set of memory cells;
- a local bit line coupled to the set of memory cells;
- and
- a keeper having variable strength coupled to the local bit line, where the keeper strength is a function of data stored in the set of memory cells.
1 more element
A memory device having an evaluation phase and a pre-charge phase, the device comprising:
- a set of memory cells;
- a local bit line connected to the set of memory cells to provide a voltage indicative of a state of one memory cell in the set of memory cells during a read operation performed on the one memory cell;
- and
- a keeper to maintain the local bit line in a charged state during a pre-charge phase and during an evaluation phase when no read operation is performed on the set of memory cells, and during an evaluation phase if not conditionally discharged by the one memory cell during a read operation;
- the keeper comprising a set of keeper control ports, each keeper control port having a keeper control voltage, so that the keeper has a variable strength controlled by the keeper control voltages.
2 more elements
A memory device comprising:
- a set of memory cells;
- a local bit line connected to the set of memory cells;
- a keeper connected to the local bit line, the keeper comprising a set of keeper control ports each having a keeper control voltage;
- and
- a data counting logic to provide the keeper control voltages to control the strength of the keeper.
2 more elements
Dependencies are inferred from the claim text.