US 2003/0112675 A1 · Semiconductor memory device · patentgrep

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Abstract

In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectively operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.

Claims26

Dependent claims

A semiconductor memory device comprising:

a first spare element provided for each of a plurality of units of a memory cell array;
second spare elements in addition to the plurality of units;
and
circuits for selectively assigning the second spare elements to arbitrary units of the plurality of units.

1 more element

A semiconductor memory device comprising:

a plurality of normal banks formed by dividing a memory cell array into a plurality of sections;
first redundant cell arrays collectively provided for one spare bank so as to be substituted for a defect memory cell of the memory cell array;
a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks;
normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address;
a first spare decoder for selectively operating the plurality of first redundant cell arrays;
a plurality of second spare decoders for selectively and correspondingly operating the plurality of second redundant cell arrays;
a first substitution-control signal line for supplying a first substitution-control signal for controlling the operation of the first spare decoder;
a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of second spare decoders;
a plurality of first memory circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored to selectively output the first substitution-control signal or the second substitution-control signal in accordance with a detection result of the correspondence between the stored address of the defect memory cell and the input address and information of the correspondence with the first redundant cell array or the second redundant cell array;
and
a control circuit for controlling the normal decoder to be deactivated state when either of the first substitution-control signal line or the second substitution-control signal line is in an active state.

8 more elements

A semiconductor memory device comprising:

a plurality of normal banks formed by dividing a memory cell array into a plurality of sections;
a plurality of first redundant cell arrays provided for a plurality of spare banks so as to be substituted for a defect memory cell of the memory cell array;
a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks;
normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address;
a plurality of first spare decoders corresponding to the plurality of the first redundant cell arrays to select and operate the plurality of the first redundant cell arrays;
a plurality of second spare decoders corresponding to the plurality of the second redundant cell arrays to select and operate the plurality of the second redundant cell arrays;
a plurality of first substitution-control signal lines for supplying a first substitution-control signal for alternatively controlling the operation of the plurality of the first spare decoders;
a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of the second spare decoders;
a plurality of first memory circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored to selectively output the first substitution-control signal or the second substitution-control signal in accordance with a detection result of the correspondence between the stored address of the defect memory cell and the input address and information of the correspondence with the first redundant cell array or the second redundant cell array;
and
a control circuit for controlling the normal decoder to be deactivate when the plurality of first substitution-control signal lines or the second substitution-control signal lines are active.

8 more elements

A semiconductor memory device comprising:

a plurality of normal banks formed by dividing a memory cell array into a plurality of sections;
a plurality of first redundant cell arrays collectively provided for one spare bank so as to be substituted for a defect memory cell of the memory cell array;
a plurality of second redundant cell arrays provided to correspond to the plurality of normal banks;
normal decoders provided to correspond to the normal banks and arranged to select the row and column of the memory cell array in accordance with an input address;
a plurality of first spare decoders corresponding to the plurality of the first redundant cell arrays to select and operate the plurality of the first redundant cell arrays;
a plurality of second spare decoders corresponding to the plurality of the second redundant cell arrays to select and operate the plurality of the second redundant cell arrays;
a plurality of first substitution-control signal lines for supplying a first substitution-control signal for correspondingly and selectively operating the plurality of first spare decoders;
a second substitution-control signal line for supplying a second substitution-control signal for controlling the operation of the plurality of second spare decoders;
a plurality of first memory circuits including first storage circuits which are provided to correspond to the plurality of first substitution-control signal lines and in which the address of a defect memory cell is previously stored and structured to selectively output the first substitution-control signal to the corresponding first substitution-control signal line in accordance with a detection result of the correspondence between the address of the defect memory cell stored in the first storage circuits and the input address;
a plurality of second memory circuits including second storage circuits in which information of the address of a defect memory cell and information as to which of the first redundant cell array and the second redundant cell array corresponds to each of the plurality of first memory circuits are previously stored and arranged to selectively output the second substitution-control signal to the second substitution-control signal line in accordance with a detection result of the correspondence between the address of the defect memory cell stored in the second storage circuits and the input address and information of the correspondence with the plurality of second redundant cell arrays;
and
a control circuit for controlling the normal decoder to be deactivate when the plurality of first substitution-control signal lines or the second substitution-control signal line is active.

9 more elements

A semiconductor memory device comprising:

a plurality of memory banks which are formed by dividing a memory cell array into a plurality of sections and each of which is constituted by a plurality of sub-arrays;
a plurality of spare elements which are provided for each of the sub-arrays and arranged to be substituted for a defect memory cell;
a plurality of normal decoders which are provided to correspond to each of the sub-arrays and arranged to select the row of the sub-array in accordance with an input address;
a plurality of spare decoders which are provided to correspond to each of the sub-arrays and arranged to correspondingly operate the plurality of spare elements;
a plurality of bank selecting lines for selecting and instructing the plurality of memory banks;
a plurality of normal-decoder control lines provided to correspond to the sets composed of a plurality of sub-arrays constituting the plurality of memory banks and arranged to select and instruct the normal decoders of the normal decoders and the spare decoders provided to correspond to the sub-arrays of each set;
a plurality of spare-decoder control lines provided to correspond to the sets composed of the plurality of sub-arrays constituting the plurality of memory banks and arranged to select and instruct the spare decoders of the normal decoders and the spare decoders provided to correspond to the sub-arrays of each set;
a plurality of spare-decoder selecting lines for alternatively selecting and controlling the plurality of spare decoders of each sub-array;
and
assigning circuits for selectively assigning the spare element of each sub-array to another sub-array belonging to the same bank.

7 more elements

A semiconductor memory device comprising:

a memory bank formed by dividing a memory cell array into a plurality of sections;
a plurality of spare elements which are provided for each memory bank and arranged to be substituted for defect memory cells;
a plurality of normal decoders disposed to correspond to the memory banks and arranged to select the row of the memory bank in accordance with an input address;
a plurality of spare decoders provided to correspond to the memory banks and arranged to correspondingly operate the plurality of spare elements;
a plurality of bank selecting lines for selectively instructing the plurality of memory banks;
a spare-decoder control line for selectively instructing the spare decoder of the normal decoders and the spare decoders;
a plurality of spare-decoder selecting lines for alternatively and selectively controlling the spare decoders of each memory bank;
and
assigning circuits provided by a number smaller than the total number of the spare elements and arranged to arbitrarily select and substitute one or plurality of spare elements for the defect memory cell.

6 more elements

Dependencies are inferred from the claim text.