Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell group comprising a plurality of memory cells grouped into a plurality of cell blocks arranged in matrix;
• selection means for outputting a selection signal provided based on a basic clock signal provided consecutively from an external section and an address signal for specifying an address of the cell block in order to select and activate the cell block by interleaving consecutively the memory cell blocks;
• specification means for specifying sequentially and activating the memory cells addressed by consecutive addresses in the memory cell block in accordance with the address signal and the selection signal for activating and enterring the cell block in an active state by the selection means;
• data input/output (I/O) means for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification means under a control based on a read-out/write-in signal provided from an external section;
• count means for counting the number of cycles of the basic clock signal provided from an external section;
• and
• control means for receiving at least one or more specification signals provided from an external section,
• for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and
• for instructing the count means to count the number of counts of the basic clock signal based on the control signal, and for controlling a selection and activation operation executed by the selection means, a specification operation executed by the specification means and the data I/O operation executed by the data I/O means, so that the memory access operations for the memory cell group are controlled.

A semiconductor memory device, comprising:

• a memory cell group comprising a plurality of memory cells arranged in matrix;
• specification means for specifying and activating at once a fixed number of the memory cells, as a package memory cell, addressed by consecutive addresses in the memory cells in accordance with a basic clock signal and an address signal provided from an external section;
• store means for storing temporarily data from or to the fixed number of the memory cells specified at the same time by the specification means;
• control means for carrying out at once a data transfer operation between the fixed number of the memory cells specified by the specification means and the store means in accordance with the basic clock signal and the specification signal;
• data input/output (I/O) means for executing sequentially a data read-out/write-in operation (data I/O operation) for the store means in accordance with the basic clock signal;
• and
• count means for counting the number of cycles of a basic clock signal,
• wherein the control means receives at least one or more specification signals provided from an external section,
• outputs a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal,
• instructs the count means to count the number of counts of the basic clock signal based on the control signal,
• controls a specification operation executed by the specification means and the data I/O operation of the data I/O means based on the number of the cycles including the number of the cycles at least two or more counted from the particular cycle by the count means, and
• so that the control means controls the memory access operations for the memory cell group.