Content addressable memory cell techniques
AssigneeBroadcom Corporation
InventorsMorteza Cyrus Afghahi, Bibhudatta Sahoo
Life of this patent
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Abstract
A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point (35) and a second bit of complementary data at a second point (36). A first transistor (40) comprising a first gate (42) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (14 and 16). Second and third transistors (50, 60) comprise gates (52, 62) coupled to the first line (14) and second line (16) and comprise circuit paths (54, 56, 64, 66) coupling the first and second points to the first gate.
Claims13
In a content addressable memory cell including a circuit operating from a predetermined supply voltage for storing a first bit of data at a first point and a second bit of data at a second point, the second bit of data being the complement of the first bit of data, apparatus for comparing the first bit of data and the second bit of data with a third bit of test data transmitted on a first line and a fourth bit of test data transmitted on a second line, the fourth bit of data being the complement of the third bit of data, said apparatus comprising in combination:
- a first transistor comprising a first gate and also comprising a first circuit path switchable to a first state in response to a first predetermined relationship between the first and second bits and the third and fourth bits and switchable to a second state in response to a second predetermined relationship between the first and second bits and the third and fourth bits;
- a second transistor comprising a second gate coupled to the first line and comprising a second circuit path coupling the first point to the first gate;
- and
- a third transistor comprising a third gate coupled to the second line and comprising a third circuit path coupling the second point to the first gate.
In a content addressable memory cell including a circuit operating from a predetermined supply voltage and a predetermine reference potential for storing a first bit of data and a second bit of data, the second bit of data being the complement of the first bit of data, a method of comparing the first bit of data and the second bit of data with a third bit of test data transmitted on a first line and a fourth bit of test data transmitted on a second line, the fourth bit of data being the complement of the third bit of data, said method employing a switching transistor comprising a gate, said method comprising in combination:
- generating a first switching voltage substantially corresponding to the supply voltage in response to a first predetermined relationship between the first and second bits and the third and fourth bits while drawing substantially no current from the first line and second line;
- generating a second switching voltage substantially corresponding to the reference potential in response to a second predetermined relationship between the first and second bits and the third and fourth bits while drawing substantially no current from the first line and second line;
- transmitting the first switching voltage to the gate of the switch transistor in response to the first predetermined relationship;
- and
- transmitting the second switching voltage to the gate of the switch transistor in response to the second predetermined relationship.
Dependencies are inferred from the claim text.