US 2003/0112671 A1 · Flash memory device with a variable erase pulse

Abstract

A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase pulse to the flash cell, and reading the flash cell. For each time the flash cell is read and is not in an erased state, the method includes applying a short erase pulse to the flash cell, counting the short erase pulse, and reading the flash cell. Finally, a length of the long erase pulse is adjusted based on the counted number of short erase pulses that were applied to the flash cell. The length of the long erase pulse may be increased if the counted number of short erase pulses is more than a high number of pulses, or it may be decreased if the counted number of short erase pulses is less than a low number of pulses. The length of the long erase pulse may be adjusted based on a past average of short erase pulses applied to the flash cell, or a quantity representing short erase pulses applied to the flash cell over a selected number of prior erases of the flash cell. The flash memory device may have a control circuit with elements to implement the method.

Claims76

Dependent claims

A method of operating a flash memory device comprising:

selecting a flash cell in a flash memory device to undergo an erase;
applying a long erase pulse to the flash cell;
reading the flash cell;
for each time the flash cell is read and is not in an erased state:
applying a short erase pulse to the flash cell;
counting the short erase pulse;
and
reading the flash cell;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cell.

7 more elements

A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;
selecting a flash cell in the flash memory device to undergo an erase based on the signals;
applying a long erase pulse to the flash cell;
reading the flash cell;
for each time the flash cell is read and is not in an erased state:
applying a short erase pulse to the flash cell;
counting the short erase pulse;
and
reading the flash cell;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cell.

8 more elements

A method of operating a flash memory device comprising:

selecting a plurality of flash cells in a flash memory device to undergo an erase;
applying a long erase pulse to the flash cells;
reading the flash cells;
for each time the flash cells are read and are not in an erased state:
applying a short erase pulse to the flash cells;
counting the short erase pulse;
and
reading the flash cells;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells.

7 more elements

A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;
selecting a plurality of flash cells in the flash memory device to undergo an erase based on the signals;
applying a long erase pulse to the flash cells;
reading the flash cells;
for each time the flash cells are read and are not in an erased state:
applying a short erase pulse to the flash cells;
counting the short erase pulse;
and
reading the flash cells;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells.

8 more elements

A method of operating a flash memory device comprising:

selecting a plurality of flash cells in a flash memory device to undergo an erase;
applying a long erase pulse to the flash cells;
reading the flash cells;
for each time the flash cells are read and are not in an erased state:
applying a short erase pulse to the flash cells;
counting the short erase pulse;
and
reading the flash cells;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells comprising:
increasing a length of the long erase pulse if the counted number of short erase pulses is more than a high number of pulses;
and
decreasing the length of the long erase pulse if the counted number of short erase pulses is less than a low number of pulses.

10 more elements

A method of operating a flash memory device comprising:

selecting a plurality of flash cells in a flash memory device to undergo an erase;
applying a long erase pulse to the flash cells;
reading the flash cells;
for each time the flash cells are read and are not in an erased state:
applying a short erase pulse to the flash cells;
counting the short erase pulse;
and
reading the flash cells;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells comprising:
calculating a quantity representing short erase pulses applied to the flash cells over a selected number of prior erases of the flash cells and the erase of the flash cells including the counted number of short erase pulses;
increasing a length of the long erase pulse if the quantity is more than a high limit;
and
decreasing the length of the long erase pulse if the quantity is less than a low limit.

11 more elements

A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;
selecting a plurality of flash cells in the flash memory device to undergo an erase based on the signals;
applying a long erase pulse to the flash cells;
reading the flash cells;
for each time the flash cells are read and are not in an erased state:
applying a short erase pulse to the flash cells;
counting the short erase pulse;
and
reading the flash cells;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells comprising:
increasing a length of the long erase pulse if the counted number of short erase pulses is more than a high number of pulses;
and
decreasing the length of the long erase pulse if the counted number of short erase pulses is less than a low number of pulses.

11 more elements

A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;
selecting a plurality of flash cells in the flash memory device to undergo an erase based on the signals;
applying a long erase pulse to the flash cells;
reading the flash cells;
for each time the flash cells are read and are not in an erased state:
applying a short erase pulse to the flash cells;
counting the short erase pulse;
and
reading the flash cells;
and
adjusting a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells comprising:
calculating a quantity representing short erase pulses applied to the flash cells over a selected number of prior erases of the flash cells and the erase of the flash cells including the counted number of short erase pulses;
increasing a length of the long erase pulse if the quantity is more than a high limit;
and
decreasing the length of the long erase pulse if the quantity is less than a low limit.

12 more elements

An information handling system comprising:

a flash memory device comprising:
an address circuit to select a plurality of flash cells in the flash memory device to undergo an erase;
and
a control circuit comprising elements to:
apply a long erase pulse to the flash cells;
read the flash cells;
for each time the flash cells are read and are not in an erased state:
apply a short erase pulse to the flash cells;
count the short erase pulse;
and
read the flash cells;
and
adjust a length of the long erase pulse based on the counted number of short erase pulses that were applied to the flash cells;
a processor;
a display unit;
an input/output subsystem;
and
a bus coupled to the processor, the flash memory device, the display unit, and the input/output subsystem.

15 more elements

Dependencies are inferred from the claim text.

Flash memory device with a variable erase pulse

Life of this patent

Flash memory device with a variable erase pulse

Life of this patent

Abstract

Claims76