Memory device with support for unaligned access

Memory system comprising m memory banks, each memory bank having an n-bit input/output interface, wherein each of at least m-1 memory banks comprise a plurality of data lines and a plurality of decoders being associated to each data line, wherein each decoder generates an enable signal upon receiving of its associated address signal, a plurality of multiplexers having two inputs and an output associated to each data line, wherein the enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.

Integrated memory block comprising a plurality of data lines and a plurality of decoders associated to each data line, whereby each decoder decodes an associated address and generates an enable signal, a plurality of multiplexers for rerouting said enable signal to either said associated data line or to the next higher data line.

Memory unit comprising a plurality of word lines and a plurality of bit lines arranged in a matrix, wherein each cross point comprises a memory cell, a plurality of word line decoders having a decoder output associated to each word line and a plurality of multiplexers each comprising two inputs and an output associated with each word line, wherein each multiplexer is coupled with the output of its associated decoder and with the output of the decoder for the next lower addressed word line, wherein the output of said multiplexers controls each associated word line and wherein the multiplexers are controlled by a select signal.