Semiconductor storage device

(Amended) An input circuit which supplies a first address signal to a predetermined circuit, which operates in response to the first address signal, comprising:

• a latch circuit which latches an input address signal for a predetermined period and outputs the first address signal to the predetermined circuit;
• a timing setting circuit which cancels the latch state of the latch circuit after a timing at which noise can be generated inside a chip;
• and
• a sense circuit which senses data stored in memory cells,
• wherein the timing setting circuit cancels the latch state of the latch circuit after a timing of activating the sense circuit in the final refresh of a predetermined number of consecutive refreshes of the memory cells.

(New) An input circuit which latches an input address signal at a predetermined timing, comprising:

• a timing setting circuit which cancels the latch state after a timing at which noise can be generated inside a chip;
• and
• a sense circuit which senses data stored in memory cells,
• wherein the timing setting circuit cancels the latch state after a timing of activating the sense circuit during a refresh of the memory cells.