US 2003/0112662 A1 · Nonvolatile semiconductor memory having page mode with a plurality of banks · patentgrep

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Abstract

A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

Claims40

Dependent claims

A nonvolatile semiconductor memory comprising:

first and second nonvolatile memory banks;
a data-line for read and a data-line for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, said data-line for read and said data-line for program and verify being shared between said first and second nonvolatile memory banks;
a sense amplifier for read connected to said data-line for read;
a sense amplifier for program and verify connected to said data-line for program and verify;
and
a program circuit connected to said data-line for program and verify.

3 more elements

A nonvolatile semiconductor memory comprising:

a nonvolatile memory block matrix in which a plurality of nonvolatile memory blocks are arrayed in a matrix in X and Y directions, each of said plurality of nonvolatile memory blocks having a first nonvolatile memory element, a first word-line and a first bit-line connected to said first nonvolatile memory element, a first row decoder connected to said first word-line, a first column decoder connected to said first bit-line, and a block decoder connected to said first row decoder and said first column decoder;
a second word-line connected to said first row decoder;
a second bit-line connected to said first column decoder;
a second row decoder connected to said second word-line;
second and third column decoders connected to said second bit-line;
a first data-line connected to said second column decoder;
a second data-line connected to said third column decoder;
a first sense amplifier connected to said first data-line;
and
a second sense amplifier connected to said second data-line.

7 more elements

A nonvolatile semiconductor memory comprising:

first and second nonvolatile memory banks, each of said first and second nonvolatile memory banks having a first word-line, a first row decoder connected to said first word-line, a first bit-line, and first and second column decoders connected to said first bit-line;
nonvolatile memory block matrices which are respectively arranged in said first and second nonvolatile memory banks and have a plurality of nonvolatile memory blocks arrayed in a matrix in X and Y directions, each of said plurality of nonvolatile memory blocks having a first nonvolatile memory element, a second word-line and a second bit-line connected to said first nonvolatile memory element, a second row decoder connected to said first and second word-lines, a third column decoder connected to said first and second bit-lines, and a block decoder connected to said second row decoder and said third column decoder;
a first data-line commonly connected to said first column decoder of said first nonvolatile memory bank and said first column decoder of said second nonvolatile memory bank;
a second data-line connected to said second column decoder of said first nonvolatile memory bank and said second column decoder of said second nonvolatile memory bank;
a first sense amplifier connected to said first data-line;
and
a second sense amplifier connected to said second data-line.

4 more elements

A nonvolatile semiconductor memory comprising:

a nonvolatile memory block matrix in which a plurality of nonvolatile memory blocks are arrayed in a matrix in X and Y directions, each of said plurality of memory blocks having a first nonvolatile memory element, a first redundancy nonvolatile memory element, a first word-line and a first bit-line connected to said first nonvolatile memory element, said first word-line and a first redundancy bit-line connected to said nonvolatile memory element, a first row decoder connected to said first word-line, a first column decoder connected to said first bit-line and said first redundancy bit-line, and a block decoder connected to said first row decoder and said first column decoder;
a second word-line connected to said first row decoder;
a second bit-line and a second redundancy bit-line connected to said first column decoder;
a second row decoder connected to said second word-line;
second and third column decoders connected to said second bit-line and said second redundancy bit-line;
a first data-line and a first redundancy data-line connected to said second column decoder;
a second data-line and a second redundancy data-line connected to said third column decoder;
a first sense amplifier connected to said first data-line and said first redundancy data-line;
and
a second sense amplifier connected to said second data-line and said second redundancy data-line.

7 more elements

A nonvolatile semiconductor memory comprising:

first and second nonvolatile memory banks, each of said first and second nonvolatile memory banks having a first word-line, a first row decoder connected to said first word-line, a first bit-line, a first redundancy bit-line, and first and second column decoders connected to said first bit-line and said first redundancy bit-line;
nonvolatile memory block matrices which are respectively arranged in said first and second nonvolatile memory banks and have a plurality of nonvolatile memory blocks arrayed in a matrix in X and Y directions, each of said plurality of nonvolatile memory blocks having a first nonvolatile memory element, a first redundancy nonvolatile memory element, a second word-line and a second bit-line connected to said first nonvolatile memory element, a second word-line and a second redundancy bit-line connected to said first redundancy nonvolatile memory element, a second row decoder connected to said first and second word-lines, a third column decoder connected to said second bit-line and said second redundancy bit-line, and a block decoder connected to said second row decoder and said third column decoder;
a first data-line commonly connected to said first column decoder of said first nonvolatile memory bank and said first column decoder of said second nonvolatile memory bank;
a second data-line connected to said second column decoder of said first nonvolatile memory bank and said second column decoder of said second nonvolatile memory bank;
a first sense amplifier connected to said first data-line;
and
a second sense amplifier connected to said second data-line.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/233,133Filed 30 Aug 2002
Priority: JP 2001-26502231 Aug 2001
Published: 19 Jun 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 29/70
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: masking faults in memories by using…

Family

US 6,671,203 B2Related patent
US 2003/0112662 A1This patent

From the US filing history. Foreign family members aren’t listed.

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