Magneto-resistive memory array
AssigneeMicron Technology, Inc.
InventorsYong Lu, Theodore Zhu, Romney R. Katti
Life of this patent
Estimating the term…
Abstract
A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.
Claims19
A memory cell, comprising:
- a first multi-resistive state bit having a first end and a second end;
- a first bit line connected to the first end of the first multi-resistive-state bit;
- a first switch coupled to the second end of the first multi-resistive-state bit which selectively provides a path for a first sense current to flow from the first bit line, through at least part of the first multi-resistive-state bit, and to a first predetermined voltage terminal that is coupled to ground;
- a second multi-resistive-state bit having a first end and a second end;
- a second bit line connected to the first end of the second multi-resistive-state bit;
- and
- a second switch coupled to the second end of the second multi-resistive-state bit which selectively provides a path for a second sense current to flow from the second bit line, through at least part of the second multi-resistive-state bit, and to a second predetermined voltage terminal.
A method for reading the state of a memory cell having a first multi-resistive-state bit with a first end and a second end and a second multi-resistive-state bit with a first end and a second end, the second end of the first multi-resistive-state bit and the second end of the second multi-resistive-state bit are selectively coupled to a predetermined reference voltage via a switch, and the first end of the first multi-resistive-state bit is coupled to a first bit line and the first end of the second multi-resistive-state bit is coupled to a second bit line, the method comprising:
- providing a sense current to the first bit line and the second bit line;
- enabling the switch to draw at least a portion of the sense current through the first multi-resistive-state bit and the second multi-resistive-state bit;
- and
- sensing the voltage difference between the first bit line and the second bit line.
A method of manufacturing a memory cell, the method comprising:
- providing a first magneto-resistive bit and a second magneto-resistive bit;
- forming a first path for a first sense current to flow through at least part of the first magneto-resistive bit to a first predetermined voltage terminal that is coupled to ground, the first path adapted to be selectively switched open or closed;
- and
- forming a second path for a second sense current to flow through at least part of the second magneto-resistive bit to a second predetermined voltage terminal, the second path adapted to be selectively switched open or closed.
A method of manufacturing a memory cell, the method comprising:
- providing a first multi-resistive state bit and a second multi-resistive state bit;
- forming a first path for a first sense current to flow through at least part of the first multi-resistive state bit to a first predetermined voltage terminal that is coupled to ground, the first path adapted to be selectively switched open or closed;
- and
- forming a second path for a second sense current to flow through at least part of the second multi-resistive state bit to a second predetermined voltage terminal, the second path adapted to be selectively switched open or closed.
Dependencies are inferred from the claim text.