Semiconductor memory
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKoji Nii
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
Claims20
A semiconductor memory having a memory cell containing first and second inverters subjected to cross connection,
- a first conductivity type being defined by first kind, and a second conductivity type being defined by second kind, wherein
- said first inverter consists of a first field effect transistor of the first kind and a first field effect transistor of the second kind,
- said second inverter consists of a second field effect transistor of the first kind and a second field effect transistor of the second kind, and
- said first and second field effect transistors of the first kind are disposed in separate first and second well regions of the second kind, respectively.
Dependencies are inferred from the claim text.