System and method for inhibiting imprinting of capacitor structures of a memory
AssigneeMicron Technology, Inc.
InventorsCem Basceri, F. Daniel Gealy
Life of this patent
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Abstract
A system and method for inhibiting the imprinting of capacitor structures employed by memory cells by occasionally changing charge states of the capacitors to a complementary charge state.
Claims37
In a memory device having an array of memory cells, a method comprising:
- storing charge in a memory cell of the array corresponding to a first state;
- and
- periodically storing charge in the memory cell corresponding to a second state complementary to the first state.
In a memory device having an array of memory cells, a method comprising:
- determining a charge state of at least one memory cell;
- and
- storing a complementary charge state in each of the memory cells for which the charge state was determined.
A method for reducing imprinting of a ferroelectric memory cell, comprising:
- periodically applying a bias to the ferroelectric memory cell to place the ferroelectric memory cell into a complementary charge state.
A method for reducing imprinting of an array of ferroelectric memory cells, comprising:
- periodically applying a bias to the ferroelectric memory cells of the array to place each ferroelectric memory cell into a complementary charge state.
In a memory device having an array of memory cells, a method comprising:
- determining a charge state of a memory cell of the array;
- and
- writing data to the memory cell corresponding to a complementary charge state.
A method for reducing imprinting of a capacitor having a dielectric formed from a ferroelectric material, the method comprising:
- applying a bias to the capacitor to change the charge state of the capacitor to a complementary charge state.
A memory device, comprising:
- an array of memory cells;
- read/write circuit coupled to the array of memory cells for reading data from and writing data to the memory cells;
- complementary charge state circuitry coupled to the read/write circuit for sensing an original charge state of the memory cells and providing a complementary charge state to the read/write circuit to be written to the respective memory cells;
- a register coupled to the complementary charge state circuitry and the read/write circuit to store an indicator of whether the charge state of the memory cells of the array are storing the original charge state or the complementary charge state;
- and
- a logic circuit coupled to the read/write circuit to provide output data from a memory cell based on the data of the memory cell and the indicator.
A memory device having an array of ferroelectric memory cells, comprising:
- read/write circuit coupled to the array of ferroelectric memory cells for reading data from and writing data to the ferroelectric memory cells;
- complementary charge state circuitry coupled to the read/write circuit for sensing an original charge state of the ferroelectric memory cells and providing a complementary charge state to the read/write circuit to be written to the respective ferroelectric memory cells;
- a dedicated ferroelectric capacitor coupled to the complementary charge state circuitry and the read/write circuit to store a charge state corresponding to whether the charge state of the memory cells of the array are storing the original charge state or the complementary charge state;
- and
- a logic circuit coupled to the read/write circuit and the dedicated ferroelectric capacitor to provide output data from a ferroelectric memory cell based on the data of the ferroelectric memory cell and the charge state of the dedicated ferroelectric capacitor.
Dependencies are inferred from the claim text.