Nonvolatile ferroelectric memory device and method for storing multiple bit using the same
AssigneeHynix Semiconductor Inc.
InventorHee Bok Kang
Life of this patent
Estimating the term…
Abstract
A nonvolatile ferroelectric memory device and a method for writing and reading multiple-bit data using the same, in which multiple bit data is stored in one cell to reduce a cell layout area, thereby obtaining price competitiveness of a chip. The nonvolatile ferroelectric memory device includes a sensing amplifier block having multiple sensing amplifiers comparing multiple-level signals from main bitlines and sensing them in a multiple-bit, the sensing amplifiers being commonly used in a multiple cell array blocks to feed the sensed multiple-bit levels back and restore them in a cell, and switching transistors arranged one by one per sub bitline to sense data values of the unit cell.
Claims27
A nonvolatile ferroelectric memory device comprising:
- a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells;
- a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column;
- a plurality of sub bitlines connected with one terminal of the unit cells to induce a voltage in the unit cells and arranged along the main bitlines;
- a sensing amplifier block comprising a plurality of sensing amplifiers comparing multiple-level signals from the main bitline and sensing them in a multiple-bit state, the sensing amplifiers being commonly used in the cell array blocks to feed the sensed multiple-bit states back and restore them in the cells;
- and
- switching transistors respectively arranged per sub bitline to current-sense multiple-level data values of the unit cells by controlling a current flow depending on multiple-level voltages induced in the sub bitline and transmitting the multiple-level voltages to the main bitlines, each of the switching transistors having a gate connected with the sub bitlines, a drain connected with the main bitlines, and a source connected with a ground voltage terminal.
A method for writing multiple-bit data, which comprises:
- providing a nonvolatile ferroelectric memory device comprising a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells controlled by a plate line and a wordline, a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column, a plurality of sub bitlines connected with one terminal of the unit cells and arranged along the main bitlines, switching transistors respectively arranged per sub bitline so that a gate is connected to the sub bitlines and a drain is connected to the main bitlines, and a sensing amplifier block consisting of a plurality of sensing amplifiers commonly used in the cell array blocks, transferring voltages corresponding to the data stored in the cells to the main bitlines by current sensing through the switching transistors and sensing the voltages transferred to the main bitlines in a multiple-bit state;
- writing high data in all the cells;
- and
- controlling voltages of the plate line and the sub bitlines to write multiple-bit data of n-bit in the cells.
A method for reading multiple-bit data, comprising:
- providing a nonvolatile ferroelectric memory device comprising a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells controlled by a plate line and a wordline, a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column, a plurality of sub bitlines connected with one terminal of the unit cells and arranged along the main bitlines, switching transistors respectively arranged per sub bitline so that a gate is connected to the sub bitlines and a drain is connected to the main bitlines, and a sensing amplifier block consisting of a plurality of sensing amplifiers commonly used in the cell array blocks to sense voltages transferred to the main bitlines;
- comparing a voltage value of a multiple-level transferred to the main bitlines with an output value of 2n−1 reference generators through first to (2n−1)th sensors;
- encoding output signals of the sensors and outputting the encoded signals in n-bit;
- and
- decoding a data value of the encoded n-bit, digital-to-analog converting the decoded value and restoring the resultant value to the cells through the main bitlines and the sub bitline.
Dependencies are inferred from the claim text.