Ball grid array chip packages having improved testing and stacking characteristics

A method of constructing at least one ball grid array semiconductor package having a substrate and a semiconductor device comprising:

• providing a substrate having a first surface, a second surface, and an aperture extending from the first surface through the substrate to the second surface;
• providing a plurality of substrate bond pads on at least one of the first surface and the second surface of the substrate in proximity to the aperture;
• providing a plurality of connective elements on at least one of the first surface and the second surface of the substrate, the plurality of connective elements being arranged in a preselected grid array pattern;
• providing a plurality of test pads on at least one of the first surface and the second surface of the substrate on a severable peripheral portion of the substrate, the plurality of test pads being arranged in a preselected pattern;
• providing the substrate with a first plurality of circuit traces, at least one of the provided circuit traces of the first plurality of circuit traces electrically connecting a substrate bond pad selected from the plurality of substrate bond pads with a connective element selected from the plurality of connective elements;
• providing the substrate with a second plurality of circuit traces, at least one of the provided circuit traces of the second plurality of circuit traces electrically connecting a test pad selected from the plurality of test pads;
• attaching at least one semiconductor device having an active surface and a plurality of bond pads thereon to one of the first surface and the second surface of the substrate;
• and
• establishing electrical connections between selected bond pads of the plurality of bond pads on the active surface of the at least one semiconductor device with selected substrate bond pads of the plurality of substrate bond pads to establish respective electrical connections therebetween.