Solid state imaging apparatus
AssigneeKabushiki Kaisha Toshiba
InventorNagataka Tanaka
Life of this patent
Estimating the term…
Abstract
A solid state imaging apparatus having a plurality of unit pixels, each pixel including a photodiode and a first readout transistor connected to the photodiode, a monitor including a monitor resistor, configured to measure a depletion potential of the monitor resistor, and a readout voltage generator configured to generate a readout voltage to be applied to a first control electrode of the first readout transistor based on the depletion potential. The monitor resistor has the same impurity concentration distribution as that of the photodiode.
Claims20
A solid state imaging apparatus comprising:
- a plurality of unit pixels, each pixel including:
- a photodiode;
- and
- a first readout transistor connected to the photodiode;
- a monitor including a monitor resistor having the same impurity concentration distribution as that of the photodiode, configured to measure a depletion potential of the monitor resistor;
- and
- a readout voltage generator configured to generate a readout voltage to be applied to a first control electrode of the first readout transistor based on the depletion potential.
A solid state imaging apparatus comprising:
- a plurality of unit pixels, each pixel including:
- a photodiode;
- and
- a first readout transistor connected to the photodiode;
- a monitor including a monitor resistor having the same depletion potential as that of the photodiode, configured to measure a depletion potential of the monitor resistor;
- and
- a readout voltage generator configured to generate a readout voltage to be applied to a first control electrode of the first readout transistor based on the depletion potential.
Dependencies are inferred from the claim text.