VGA quad device and apparatuses including same
AssigneeKoninklijke Philips Electronics N.V.
InventorViatcheslav Pronkine
Life of this patent
Estimating the term…
Abstract
A frame buffer (100, 300) receives N asynchronous digital video signals and generates a data stream corresponding to a single video signal representing all of the N asynchronous video signals responsive to read and write memory addresses generated by a frame buffer controller (200, 400), where N is an integer greater than or equal to 2. If desired, N can be a positive integer equal to or greater than 4. Preferably, the frame buffer includes N dual ported memory devices (110, 120, 130, 140), each or which can be written to and read from simultaneously and independently. A VGA quad device and apparatuses incorporating same are also described.
Claims16
A frame buffer receiving N asynchronous digital video signals and generating a data stream corresponding to a single video signal representing all of the N asynchronous video signals responsive to read and write memory addresses generated by a frame buffer controller, where N is an integer greater than or equal to 2.
A VGA quad device receiving N asynchronous digital video signals and generating a single video signal representing all of the N asynchronous video signals, comprising:
- a frame buffer which stores data corresponding to the single video signal;
- a controller generating write addresses permitting digital data corresponding to the N asynchronous digital video signals to be written into the frame buffer and read addresses permitting the data stored in the frame buffer to be read out as a single data block,
- where N is an integer equal to or greater that 2.
A VGA quad device receiving N asynchronous digital video signals and generating a single video signal representing all of the N asynchronous video signals, comprising:
- frame buffer means for storing data corresponding to the single video signal;
- converter means receiving the data corresponding to the single video signal for converting the data into the single video signal;
- and
- controller means for generating write addresses permitting digital data corresponding to the N asynchronous digital video signals to be written into the frame buffer and for generating read addresses permitting the data stored in the frame buffer to be output to the converter means,
- where N is an integer equal to or greater that 2.
A VGA quad device receiving N asynchronous digital video signals and generating a single video signal representing all of the N asynchronous video signals, comprising:
- N video buffers which receive N asynchronous digital video signals and which store N data groups corresponding to the N asynchronous video signals;
- a frame buffer, which stores the N data groups as data corresponding to the single video signal and outputs the data for display;
- a controller generating read/write addresses applied to the N video buffers and the frame buffer to thereby permit digital data corresponding to the N asynchronous digital video signals to be transferred from the N video buffers into the frame buffer and read addresses permitting the data stored in the frame buffer to be read out as a single data block,
- where N is an integer equal to or greater that 2.
A KVM switch having a first operating mode permitting a selected one of N asynchronous video signals to be output for display and a second operating mode permitting a single video signal corresponding to the N asynchronous video signals to be output for display, comprising:
- a first selector switch receiving the N asynchronous video signals and outputting the selected one of the N asynchronous video signals as a selected video signal;
- a frame buffer which stores data corresponding to the single video signal;
- an analog-to-digital converter, which receives the data corresponding to the single video signal and converts the data into the single video signal;
- a second selector switch which receives the output of the first video switch and the converter and outputs one of the selected video signal and the single video signal;
- and
- a controller which generates write addresses permitting digital data corresponding to the N asynchronous digital video signals to be written into the frame buffer and which generates read addresses permitting the data stored in the frame buffer to be output to the converter,
- where N is an integer equal to or greater that 2.
Dependencies are inferred from the claim text.