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AssigneeInternational Business Machines Corporation
InventorsFrancois I. Atallah, Anthony Correale JR., David J. Seman, Richard D. Tax
Estimating the term…
A precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF) and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, which causes the current starved inverter's delay to degrade/improve on only one transition to effect a change in the duty cycle. For improved precision, a differential embodiment employs the same VCDCG.
A circuit for generating an output clock signal having a desired duty cycle, comprising:
A voltage controlled duty cycle generator comprising a plurality of stages, each of which comprises a current starved inverter comprised of PFET current sources and NFET current sources followed by a series inverter which presents a capacitive load to the current sources, to provide either additive or substractive duty cycle corrections, the plurality of current starved inverters being controlled by an input control signal voltage which is connected to both the PFET current sources and the NFET current sources, and as the input control voltage increases, the PFET current sources provide a smaller current to charge the capacitive load, and the NFET current sources provide a larger current to discharge the capacitive load, such that the output waveform has a slow rising edge and a fast falling edge, and the difference in edge rates causes the output of the inverter to have a longer falling delay than a rising delay to produce a duty cycle that is controlled by the input control signal voltage.
Dependencies are inferred from the claim text.