PLL circuit and control method for PLL circuit

Abstract

A PLL circuit for reducing an error in a frequency of an output signal for a reference signal and outputting the output signal with a smaller spurious output, and a control method for the PLL circuit. The PLL circuit has: a clock generator for generating and outputting a clock signal having an oscillating frequency, on the basis of a reference input signal; a phase detector for detecting a phase difference between the clock signal and an output feedback signal, and outputting a phase difference signal; a controller for controlling an oscillating frequency of an output signal on the basis of the phase difference signal; and a divider for dividing the oscillating frequency of the output signal outputted from the controller, and outputting a dividing signal having an oscillating frequency corresponding to the oscillating frequency of the clock signal, as the output feedback signal.

Dependencies are inferred from the claim text.