Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit
AssigneeElpida Memory, Inc.
InventorTsugio Takahashi
Life of this patent
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Abstract
An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.
Claims16
An output buffer circuit for outputting data in the form of an input pulse train at a predetermined output impedance and slew rate, comprising:
- a main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data, and at least a pair of a second p-channel MOS transistor and a second n-channel MOS transistor for driving said load in coaction with said first p-channel MOS transistor and said first n-channel MOS transistor;
- a predriver having at least a pair of a third p-channel MOS transistor and a third n-channel MOS transistor for driving said first p-channel MOS transistor according to said data, at least a pair of a fourth p-channel MOS transistor and a fourth n-channel MOS transistor for driving said first n-channel MOS transistor according to said data, at least one fifth n-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third n-channel MOS transistor, and at least one fifth p-channel MOS transistor for driving said first n-channel MOS transistor in coaction with said fourth p-channel MOS transistor;
- and
- a controller for generating control signals to control said fifth n-channel MOS transistor into and out of operation in coaction with said second p-channel MOS transistor, and control said fifth p-channel MOS transistor into and out of operation in coaction with said second n-channel MOS transistor.
An output buffer circuit for outputting data in the form of an input pulse train at a predetermined output impedance and slew rate, comprising:
- a main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data, and at least a pair of a second p-channel MOS transistor and a second n-channel MOS transistor for driving said load in coaction with said first p-channel MOS transistor and said first n-channel MOS transistor;
- a predriver having at least a pair of a third p-channel MOS transistor and a third n-channel MOS transistor for driving said first p--channel MOS transistor according to said data, at least a pair of a fourth p-channel MOS transistor and a fourth n-channel MOS transistor for driving said first n-channel MOS transistor according to said data, at least one fifth n-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third n-channel MOS transistor, at least one fifth p-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third p-channel MOS transistor, at least one sixth p-channel MOS transistor for driving said first n-channel MOS transistor in coaction with said fourth p-channel MOS transistor, and at least one sixth n-channel MOS transistor for driving said first n-channel MOS transistor in coaction with said fourth n-channel MOS transistor;
- and
- a controller for generating control signals to control said fifth p-channel MOS transistor and said fifth n-channel MOS transistor into and out of operation in coaction with said second p-channel MOS transistor, and control said sixth p-channel MOS transistor and said sixth n-channel MOS transistor into and out of operation in coaction with said second n-channel MOS transistor.
Dependencies are inferred from the claim text.