5 V Tolerant hot carrier injection (HCI) protection circuit
AssigneeLSI Logic Corporation
InventorsAndrew M. Rankin, Jason Hoff, Ken Szajda
Life of this patent
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Abstract
A long channel transistor and a shorter channel transistor operate in conjunction to drive an output node. The long channel device is first activated by a drive signal and the drive signal is input to a delay element that then activates the shorter channel device. By enabling the long channel device first, hot carrier injection effects are reduced. Employing two transistors that are sized to operate in different voltage ranges reduces surge current. The two-transistor configuration of the present invention occupies less area than a single long channel device with similar drive capabilities.
Claims12
A high reliability output driver comprising:
- a first transistor having a first gate channel length and a first gate electrode, said first transistor being operatively connected between an output node and a first voltage terminal;
- a second transistor having a second gate channel length and a second gate electrode wherein said second gate channel length is greater than said first gate channel length, said second transistor being operatively connected between said output node and said first voltage terminal;
- a drive signal line connected to said first gate electrode of said first transistor;
- and
- a delay element having an input connected to said drive signal line and an output connected to said second gate electrode of said second transistor.
A method for increased reliability in a semiconductor driver comprising:
- connecting a first transistor having a first gate electrode between a voltage terminal and an output node;
- connecting a second transistor having a second gate electrode between said voltage terminal and said output node wherein said second transistor has a gate channel length that is less than the gate channel length of said first transistor;
- applying a first gating signal to said first gate electrode of said first transistor;
- applying said first gating signal to the input of a delay element to generate a delayed output;
- and
- applying said delayed output to said second gate electrode of said second transistor.
Dependencies are inferred from the claim text.