Zipper domino carry generate cell for fast adders
AssigneeIntel Corporation
InventorThomas D. Fletcher
Life of this patent
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Abstract
A differential logic stage includes a precharge circuit, a first evaluate circuit and a second evaluate circuit. The precharge circuit is connected to a first potential and a differential output defined by a first output node and a second output node. The second evaluate circuit is connected to a second potential and a first output node. The second evaluate circuit is connected to the second potential and the second output node. The second evaluate circuit is symmetric with the first evaluate circuit, and in one embodiment each evaluate circuit includes a transistor stack and an input transistor. The transistor stack is connected between the second potential and one of the output nodes. The input transistor is connected in parallel with the transistor stack.
Claims20
A logic stage comprising:
- a precharge circuit connected to a first potential and a differential output defined by a first output node and a second output node;
- a first evaluate circuit connected to a second potential and the first output node;
- and
- a second evaluate circuit connected to the second potential and the second output node, the second evaluate circuit being symmetric with the first evaluate circuit.
Implemented in a differential domino logic stage having a precharge circuit and a true evaluate circuit, a not true evaluate circuit comprising:
- a transistor stack connected between a potential and one of a pair of output nodes, the transistor stack to receive a not true generate input corresponding to a less significant bit of an adder circuit and a not true generate input corresponding to a more significant bit;
- and
- an input transistor connected in parallel with the transistor stack, the input transistor to receive a not true propagate input corresponding to the more significant bit.
Dependencies are inferred from the claim text.