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US 2003/0112032 A1Published application
Double data rate flip-flop
AssigneeXilinx, Inc.
InventorsSteven P. Young, Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun
Life of this patent
Estimating the term…
Abstract
Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
Claims8
In an FPGA having programmable interconnect and programmable clock routing, an input/output port comprising:
- a double data rate flip-flop comprising two master latches having outputs coupled to a multiplexer comprising a slave latch, the master latches and multiplexer being controlled by two clock signals substantially 180 degrees out of phase with each other such that data is alternately written from one of the two master latches into the slave latch;
- and
- a tri-state driver having an input connected to the slave latch and an output for driving signals off the integrated circuit device.
Dependencies are inferred from the claim text.