Test circuit arrangement and method for testing a multiplicity of transistors
AssigneeInfineon Technologies AG
InventorsUte Kollmer, Ulrich Schaper, Carsten Linnenbank, Roland Thewes
Life of this patent
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Abstract
The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.
Claims12
A test circuit arrangement for testing a multiplicity of transistors,
- having a multiplicity of transistors which are to be tested and which are connected to one another,
- having an electrical selector unit, connected to the transistors to be tested, for selecting at least one transistor to be tested,
- having a gate voltage source which can be connected to the gate terminal of each transistor to be tested,
- having a source voltage source which can be connected to the source terminal of each transistor to be tested,
- in which a measuring unit which is connected to the drain terminals of the transistors to be tested is provided for measuring the drain current which flows through the respectively selected transistor.
A method for testing a multiplicity of transistors which are connected to one another,
- in which a transistor to be tested is selected from the multiplicity of transistors to be tested by means of an electrical selector unit,
- in which a gate voltage, a drain voltage or a source voltage is applied to the gate, the drain or the source of the selected transistor and varies around a predefined working point of the selected transistor,
- in which the drain current which is obtained on the basis of the applied gate voltage, drain voltage or source voltage and which flows through the selected transistor is measured,
- in which the small signal behavior of the transistor to be investigated is determined from the measured drain currents and the associated applied gate voltages, drain voltages and source voltages,
- in which the steps is carried out for all those transistors of the multiplicity of transistors which are to be investigated.
Dependencies are inferred from the claim text.