Miller compensated nmos low drop-out voltage regulator using variable gain stage

A modified Miller compensated voltage regulator comprising:

• a differential amplifier input stage having a first input, a second input, and an output;
• an inverting inter-stage variable gain amplifier having an output, a first input connected to a reference voltage, and a second input coupled to the output of the differential amplifier input stage;
• a NMOS output transistor having a source, drain and gate;
• a unity gain buffer coupling the output of the inverting inter-stage variable gain amplifier to the gate of the NMOS output transistor;
• and
• a feedback capacitor coupled at a first end to the NMOS output transistor source, and coupled at a second end to the inverting inter-stage variable gain amplifier second input to form a compensation loop;
• wherein the inverting inter-stage variable gain amplifier, the unity gain buffer, the NMOS output transistor, and the feedback capacitor are responsive to a changing load current to control a unity gain bandwidth associated with the compensation loop.

A modified Miller compensated voltage regulator comprising:

• an input amplifier stage configured to receive an input reference voltage and further configured to receive a feedback current via a nested Miller compensation capacitor associated with the voltage regulator to generate a displacement current to provide an effective Miller multiplied compensating capacitance;
• an inverting inter-stage variable gain amplifier having an output pole associated therewith, the inverting inter-stage variable gain amplifier configured to receive the feedback displacement current associated with the nested Miller compensation capacitor such that the pole associated with the output of the inverting inter-stage variable gain amplifier is pushed out to a frequency above a Unity Gain Frequency associated with the compensation loop and further configured to generate an amplified displacement current signal therefrom;
• and
• an output amplifier stage having a pole associated therewith, the output amplifier stage configured to receive the amplified displacement current signal such that the pole associated with the output amplifier stage is pushed out to a frequency above the Unity Gain Frequency of the compensation loop thereby rendering the voltage regulator output stage capable of generating a stable regulated output voltage at frequencies in the vicinity of the control loop bandwidth associated with the voltage regulator.

A modified Miller compensated voltage regulator comprising:

• means comprising a power NMOS device configured for generating a feedback current;
• means for generating a displacement current from the feedback current;
• means for amplifying the displacement current such that non-dominant poles associated with the voltage regulator are pushed to frequencies outside the control loop bandwidth of the voltage regulator;
• and
• means comprising a unity gain buffer for generating output voltage signals having substantially maximized power supply ripple rejection characteristics inside the control loop bandwidth, wherein the unity gain buffer is operational to receive the displacement current and drive the power NMOS device therefrom.

A modified Miller compensated voltage regulator comprising:

• a supply voltage node;
• an output voltage node;
• a ground;
• a differential amplifier having a bias input connected to the supply voltage node, an output, an inverting input connected to a reference voltage, and a non-inverting input;
• an inverting inter-stage variable gain amplifier having an output, a reference voltage input connected to a ground reference voltage, and an inverting input in communication with the output of the differential amplifier;
• a unity gain buffer having an output, an input in communication with the output of the inverting inter-stage variable gain amplifier, and a supply voltage input configured to receive a supply voltage from a charge pump;
• an output power NMOS device having a drain connected to the supply voltage node, a source connected to the output voltage node, and a gate in communication with the output of the unity gain buffer;
• a voltage divider network having a first node connected to the power NMOS source, a second node connected to ground, and a third node connected to the differential amplifier non-inverting input to provide a feedback voltage;
• and
• a compensation capacitor connected at one end to the power NMOS device source and connected at an opposite end to the output of the differential amplifier to form a compensation loop.