Superconductor device and method of manufacturing the same

A semiconductor device comprising:

• a semiconductor substrate;
• a plurality of element regions formed in the semiconductor substrate and defined by an element separation region;
• a plurality of conductor plugs which are embedded in an interlayer insulation film that covers the semiconductor substrate having the element regions formed therein, the plurality of conductor plugs being connected to said respective element regions or conductor layers connected to said respective element regions;
• and
• a plurality of wiring layers which are formed on the interlayer insulation film and connected to said respective conductor plugs,
• wherein the conductor plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers in such a manner that the straight line and upper surfaces of the conductor plugs are superposed each other, and when the conductor plugs are viewed in a cross section parallel to a main surface of the semiconductor substrate, two sides of the sides defining each of the conductor plugs in the cross section are in parallel to a longitudinal direction of the wiring layers and in self-align with the wiring layers.

A semiconductor device comprising:

• a semiconductor substrate;
• a plurality of element regions formed in the semiconductor substrate and defined by an element separation region;
• a plurality of nonvolatile memory cells each having a source diffusion layer, a drain diffusion layer and a control gate electrode formed in the element region, the control gate being formed as a word line extending in one direction;
• a plurality of first conductor plugs which are embedded in an interlayer insulation film that covers the nonvolatile memory cells, the plurality of first conductor plugs being connected to the drain diffusion layer of one of said nonvolatile memory cells or the drain diffusion layer of one end of a series of said nonvolatile memory cells;
• a plurality of second conductor plugs which are embedded in the interlayer insulation film, the plurality of second conductor plugs being connected to the source diffusion layer of one of said nonvolatile memory cells or the source diffusion layer of one end of a series of said nonvolatile memory cells;
• a bit line which is formed on the interlayer insulation film, the bit line being connected to the first conductor plugs and arranged orthogonal to the word lines,
• wherein the first conductor plugs are arranged on a straight line orthogonal to the longitudinal direction of the bit line in the same pitch as the bit line in such a manner that the straight line and upper surfaces of the first conductor plugs are superposed each other, and the first conductor plugs each have a substantially square pattern having two sides parallel to a direction of an arrangement of the first conductor plugs and two sides parallel to the longitudinal direction of the bit line.

A method of manufacturing a semiconductor device, comprising:

• forming a plurality of element regions defined by an element separation region in a semiconductor substrate and forming an element in each of said element regions;
• forming sequentially a first barrier insulation film, an interlayer insulation film, and a second barrier insulation film on the semiconductor substrate having the element formed thereon;
• etching from the second barrier insulation film to a predetermined depth of the interlayer insulation film to form a plurality of wiring grooves aligned with said plurality of element regions;
• forming a resist pattern having a linear or wave shaped opening that crosses said plurality of wiring grooves;
• etching the interlayer insulation film and the first barrier insulation film while using the resist pattern and the second barrier insulation film as masks, to form a contact hole on each of said element regions;
• embedding a conductor plug in the contact hole;
• removing the second barrier insulation film;
• and
• embedding a wiring layer which is connected to the conductor plug in the wiring groove of the interlayer insulation film.

A method of manufacturing a semiconductor device, comprising:

• forming a plurality of element regions defined by an element separation region in a semiconductor substrate and forming an element in each of said element regions;
• forming sequentially a first barrier insulation film, a first interlayer insulation film, and a second barrier insulation film on the semiconductor substrate having the element formed thereon;
• etching the second barrier insulation film to form a stripe groove which is formed over the element regions and extends to the first interlayer insulation film;
• forming a second interlayer insulation film which is embedded in the stripe groove to flatly cover the second barrier insulation film;
• forming a resist pattern having a linear or wave shaped opening orthogonal to the stripe groove on the second interlayer insulation film;
• etching the second interlayer insulation film and the first interlayer insulation film while using the resist pattern and the second barrier insulation film as masks to form a contact hole leading to each of said element regions and at the same time a wiring groove which ends at the first barrier insulation film;
• embedding a conductor plug in the contact hole;
• and
• embedding a wiring layer which is connected to the conductor plug in the wiring groove of the second interlayer insulation film.

A semiconductor device comprising:

• a semiconductor substrate;
• stripe shaped element regions and element separation regions which are formed in the semiconductor substrate and repeatedly disposed in a first direction in a predetermined pitch;
• a memory cell unit constituted of a plurality of nonvolatile memory cells formed on the element region;
• a source diffusion layer connected to one end of a current path of the memory cell unit;
• a drain diffusion layer connected to another end of the current path of the memory cell unit;
• a bit line contact plug which is connected to the drain diffusion layer and disposed in the first direction in the same pitch as the predetermined pitch;
• and
• a wiring layer connected to the bit line contact plug, wherein two sides of the bit line contact plug orthogonal to the first direction form a substantially rectangular pattern defined in a self-align with the wiring layer.