Stacked die semiconductor device

A stacked multichip package, comprising:

• a base carrier having a top side and a bottom side;
• a bottom integrated circuit die having a top surface and a bottom, opposing surface, wherein the bottom surface of the first integrated circuit die is attached to the top side of the base carrier;
• and
• a top integrated circuit die, the top integrated circuit die having a body with a bottom surface attached to the top surface of the bottom integrated circuit die, and a top surface, the top die top surface including a plurality of bonding pads, wherein the body includes steps extending along opposing sides of the bottom surface such that an area of the bottom surface is less than an area of the top surface.

A method of making a stacked multichip package comprising the steps of:

• attaching a bottom integrated circuit die to a base carrier, the bottom die having a top surface and a bottom surface, wherein the bottom surface is attached to the base carrier and wherein the top surface has a central area and a peripheral area, the peripheral area including a plurality of first bonding pads;
• electrically connecting the bottom die to the base carrier by wirebonding first wires to the plurality of first bonding pads of the bottom die and to corresponding first leads on the base carrier;
• forming steps in a bottom surface of a top integrated circuit die, the steps being formed along a peripheral edge of the bottom surface so that the top die has a T-shaped cross-section;
• attaching the bottom surface of the top die to the central area of the bottom die top surface;
• and
• electrically connecting the top die to the base carrier by wirebonding second wires to second bonding pads located on a top surface of the top die and to corresponding second leads on the base carrier.