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US 2003/0111684 A1Published application
Semiconductor devices and methods for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorWeon-Ho Park
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AssigneeSamsung Electronics Co., Ltd.
InventorWeon-Ho Park
Estimating the term…
Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device further includes a floating junction region, a resistive junction region, and a channel junction region, which are formed in the cell active region, the resistor active region, and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region have the same thickness. A covering gate and an MROM gate cross over the resistive active region and the channel active region, respectively. Also, a memory gate and a select gate cross over the cell active region. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. A floating junction region, a resistive junction region, and a channel junction region are then formed in the cell active region, the resistor active region, and the MROM active region, respectively. Thereafter, a select gate and a memory gate are formed on the cell active region. Also, a covering gate and an MROM gate are formed on the resistor active region and the MROM active region, respectively. The floating junction region, the resistive junction region, and the channel junction region are preferably formed at the same time.
A semiconductor device comprising:
A method for fabricating a semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
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Floating-gate IGFETs: characterised by the shapes, relative sizes or dispositions of the floating gate electrode
Read-only memory [rom] devices
Doping programmed, e.g. mask ROM: channel doping programmed
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
Term end not estimated
This application relies for priority upon Korean Patent Application No. 2001-81319, filed on Dec. 19, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor devices and methods for fabricating the same and, more particularly, to semiconductor devices including nonvolatile memory transistors, resistors, and mask ROMs (MROMs) and methods for fabricating the same.
Like identification cards, credit cards, and electronic cash, applications of smart cards having multiple functions have been on the increase. Smart cards not only store data of users and transactions, but also include programs adequate for inherent functionality. Smart cards therefore comprise semiconductor devices having both nonvolatile memory transistors for recording and storing data and MROMs for storing program data. In addition, the semiconductor devices used in the smart cards further include resistors for effecting their operation.
The above and other features and advantages of the present invention will become readily apparent from the description that follows, with reference to the accompanying drawings, in which:
FIG. 1 is a cross-sectional view of a typical FLOTOX-type EEPROM.
FIG. 2 is a cross-sectional view of a typical resistor of a semiconductor device.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like elements throughout.
FIGS. 4, 5, and 6 are top plan views illustrating a FLOTOX-type EEPROM, a resistor, and an MROM transistor, respectively, according to a preferred embodiment of the present invention. In addition, FIGS. 7, 8, and 9 are perspective views illustrating the FLOTOX-type EEPROM, the resistor, and the MROM transistor, respectively, according to the preferred embodiment of the present invention.
Referring to FIGS. 4 and 7, a device isolation layer 110 is disposed at a predetermined region of a semiconductor substrate to define a cell active region where a FLOTOX-type EEPROM will be formed. A memory gate 191 and a select gate 192 are disposed to cross over the cell active region and the device isolation layer 110.