Semiconductor memory device and its manufacturing method

A semiconductor memory device comprising:

• a semiconductor layer formed on an insulating film;
• and
• a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors body regions thereof being connected in series, one side of each said memory cell being connected to a bit line and the other side of each said memory cell being supplied with a reference potential,
• wherein a threshold value of one of said transistors is controlled by controlling injection or discharge of an electric charge to or from a body region of one of said transistors of a selected memory cell, thereby to store data.

A semiconductor memory device manufacturing method comprising:

• forming an oxide layer and a silicon active layer on a semiconductor substrate;
• forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer;
• forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it;
• injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask;
• forming said paired transistors by activating the injected ions through a heat process;
• and
• forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.