Ovonic unified memory device and magnetic random access
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorShigehio Kuge
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Abstract
A semiconductor memory device capable of achieving high integration is provided. A semiconductor memory device is provided with: a silicon substrate; bipolar transistors formed on the silicon substrate; an interlayer insulating film which has contact holes accepting parts of the bipolar transistors and reaching a surface of the silicon substrate, and which is formed on the silicon substrate; and storage elements electrically connected to the bipolar transistors. The storage elements have a first state in which an electrical resistance is relatively high and a second state in which an electrical resistance is relatively low.
Claims10
A semiconductor memory device comprising:
- a semiconductor substrate;
- a junction transistor formed on said semiconductor substrate;
- an insulating layer which has a hole accepting at least part of said junction transistor and reaching a surface of said semiconductor substrate, and which is formed on said semiconductor substrate;
- and
- a storage element electrically connected to part of said junction transistor provided in said hole, wherein
- said storage element has a first state in which an electric resistance is relatively high and a second state in which an electric resistance is relatively low,
- said junction transistor includes:
- a first conductive type well region formed in said semiconductor substrate;
- a second conductive type impurity region formed in said first conductive type well region so as to face to said hole;
- and a first conductive type conductive region provided in said hole so as to be in contact with said second conductive type impurity region.
Dependencies are inferred from the claim text.