US 2003/0111677 A1 · Semiconductor device

Abstract

When a digital video signal inputted to a latch circuit is Hi electric potential, undesirably a current flows continuously for one horizontal period at maximum, and this causes a great increase in power consumption of a semiconductor device. Therefore an object of the present invention is to provide a display device in which power consumption can be reduced by minimizing occurrence of the current path during the circuit operation, as well as a driving method. The present invention provides a semiconductor device in which two outputs, a non-inverted output and an inverted output, are obtained when a digital video signal is inputted and therefore occurrence of the current path can be minimized in a downstream buffer driven by these signals. Furthermore, a semiconductor device with reduced power consumption is provided by using the structure described above.

Claims33

Dependent claims

A semiconductor device having first and second input terminals, first and second circuit, and first and second output terminals,

wherein transistors that constitute the first circuit and the second circuit all have the same polarity,
wherein the first output terminal is connected to the first circuit and the second output terminal is connected to the second circuit,
wherein a first electric potential or a second electric potential is applied to the first input terminal and the second input terminal,
wherein a through current flows in the first circuit only when the voltage applied to the first input terminal and the second input terminal is the first electric potential,
wherein, when a signal applied to the second input terminal is the first electric potential, an inverted signal of the first input signal is outputted from the first output signal and, at the same time, the first input signal is outputted from the second output signal, and
wherein, when a signal applied to the second input terminal is the second electric potential, an output from the first output terminal and an output from the second output terminal are in a floating state.

3 more elements

A semiconductor device having first and second input terminals, first and second output terminals, first through fourth transistors, and a load circuit,

wherein the load circuit has an input electrode and an output electrode,
wherein gate electrodes of the first, third, and fourth transistors are connected to the first input terminal,
wherein a gate electrode of the second transistor and an input electrode of the fourth transistor are both connected to the second input terminal,
wherein an output electrode of the first transistor and the output electrode of the load circuit are both connected to an input electrode of the third transistor,
wherein the input electrode of the load circuit is connected to a first power supply,
wherein an input electrode of the second transistor is connected to a second power supply,
wherein an output electrode of the second transistor is connected to the first input electrode,
wherein an output electrode of the third transistor is connected to the first output terminal,
wherein an output electrode of the fourth transistor is connected to the second output terminal, and
wherein the first through fourth transistors have the same conductivity type.

7 more elements

A semiconductor device having first through fourth input terminals, first through fourth output terminals, first through fourth transistors, a load circuit, and an amplitude compensating buffer circuit,

wherein the load circuit has an input electrode and an output electrode,
wherein gate electrodes of the first, third, and fourth transistors are connected to the first input terminal,
wherein a gate electrode of the second transistor and an input electrode of the fourth transistor are both connected to the second input terminal,
wherein an output electrode of the first transistor and the output electrode of the load circuit are both connected to an input electrode of the third transistor,
wherein the input electrode of the load circuit is connected to a first power supply,
wherein an input electrode of the second transistor is connected to a second power supply,
wherein an output electrode of the second transistor is connected to the first input electrode,
wherein an output electrode of the third transistor is connected to the first output terminal,
wherein an output electrode of the fourth transistor is connected to the second output terminal,
wherein the third input terminal is connected to the first output terminal,
wherein the fourth input terminal is connected to the second output terminal,
wherein the amplitude compensating buffer circuit has means for compensating amplitude attenuation of the first output terminal, means for outputting to the third output terminal, and means for compensating amplitude attenuation of the second output terminal to output to the fourth output terminal, and
wherein the first through fourth transistors have the same conductivity type.

10 more elements

A semiconductor device having first and second input terminals, first and second output terminals, first through third transistors, and a load circuit,

wherein the load circuit has an input electrode, an output electrode, and a control electrode,
wherein gate electrodes of the first and third transistors are connected to the control electrode of the load circuit and to the first input terminal,
wherein a gate electrode of the second transistor and an input electrode of the third transistor are both connected to the second input terminal,
wherein an output electrode of the first transistor and the output electrode of the load circuit are both connected to the second output terminal,
wherein an output electrode of the third transistor is connected to the first output terminal,
wherein an output electrode of the second transistor is connected to an input electrode of the first transistor,
wherein the input electrode of the load circuit is connected to a first power supply,
wherein an input electrode of the second transistor is connected to a second power supply, and
wherein the first through third transistors have the same conductivity type.

6 more elements

A semiconductor device having first through fourth input terminals, first through fourth output terminals, first through third transistors, a load circuit, and an amplitude compensating buffer circuit,

wherein the load circuit has an input electrode, an output electrode, and a control electrode,
wherein gate electrodes of the first and third transistors are connected to the control electrode of the load circuit and to the first input terminal,
wherein a gate electrode of the second transistor and an input electrode of the third transistor are both connected to the second input terminal,
wherein an output electrode of the first transistor and the output electrode of the load circuit are both connected to the second output terminal,
wherein an output electrode of the third transistor is connected to the first output terminal,
wherein an output electrode of the second transistor is connected to an input electrode of the first transistor,
wherein the input electrode of the load circuit is connected to a first power supply,
wherein an input electrode of the second transistor is connected to a second power supply,
wherein the third input terminal is connected to the first output terminal,
wherein the fourth input terminal is connected to the second output terminal,
wherein the amplitude compensating buffer circuit has means for compensating amplitude attenuation of the first output terminal, means for outputting to the third output terminal, and means for compensating amplitude attenuation of the second output terminal to output to the fourth output terminal, and
wherein the first through third transistors have the same conductivity type.

9 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims33