Circuit for controlling an AC-timing parameter of a semiconductor memory device and method thereof

A method for controlling an AC-timing parameter of a semiconductor memory device by recognizing a variation in the AC timing parameter of the semiconductor memory device and controlling the operation of the semiconductor memory device, the method comprising:

• (a) receiving an input signal and generating first through n-th (wherein n is a natural number) delay signals, each delay signal offset from the input signal by a corresponding delay time;
• (b) using the input signals and the first through n-th delay signals to generate first through n-th comparison pulse signals, each pulse signal having an active section with a corresponding to one of the delay times duration;
• and
• (c) comparing the input signals with the first through n-th comparison pulse signals and generating first through n-th operation control signals for controlling an AC-timing parameter of the semiconductor memory device.

A circuit for recognizing a cycle of a reference clock signal by recognizing a variation in an AC-timing parameter of a semiconductor memory device and for controlling the operation of the semiconductor memory device, the circuit comprising:

• an operation-determining portion to receive an input signal and an operation-enabling signal and generate an operation-determining signal;
• a delay-time-defining portion to receive the input signal and generate first and second delay signals, delayed from the input signal by a corresponding delay time;
• a comparing portion to receive the first and second delay signals and generate first and second comparison pulse signals, each having an active section with a duration corresponding to the delay time of corresponding delay signal;
• and
• a controlling portion, to receive the operation-determining signal and the first and second comparison pulse signals, compare the operation-determining signal with the first and second comparison pulse signals, and generates the first and second operation control signals based on the comparison of the operation-determining signal with the comparison pulse signals, for controlling the semiconductor memory device.

A method for operating a semiconductor device, the method comprising:

• comparing the duration of an input signal to the duration of a first internally generated comparison pulse;
• selecting a first internal operation when the input signal duration is less than the comparison pulse duration;
• and
• selecting a second internal operation when the input signal duration is greater than the comparison pulse duration.

A semiconductor memory device having a control circuit to modify the behavior of the device, the control circuit comprising:

• a first delay circuit to generate a first delayed signal in response to an input signal;
• a first pulse generator to generate a first comparison pulse, the first comparison pulse having a duration related to the delay of the first delay circuit and triggered in response to an input signal assertion;
• and
• a first duration comparator to generate a first operation control signal, the operation control signal set to a first logic state when the duration of the input signal is longer than the duration of the first comparison pulse, the operation control signal set to a second logic state when the duration of the input signal is shorter than the duration of the first comparison pulse.