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US 2003/0111672 A1Published application
Non-volatile memory and method of forming thereof
AssigneeFreescale Semiconductor, Inc.
InventorsCraig A. Cavins, Ko-Min Chang
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. Each column of the array is located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials to each column, with isolation of results for each column. In one embodiment, the memory cells are devoid of floating gate devices and use a non-conductive charge storage layer to store charges. In another embodiment, the memory cells store charges in nanocrystals.
Claims23
A semiconductor device having a non-volatile memory (NVM) array including rows and columns of memory cells comprising:
- a first well region and a second well region within a semiconductor substrate, wherein the first well region and the second well region are spaced apart and electrically isolated;
- a first column of memory cells positioned within the first well region;
- a second column of memory cells positioned within the second well region;
- a first tunnel dielectric of a first memory cell in the first column of memory cells and a second tunnel dielectric of a second memory cell in the second column of memory cells;
- a first charge storage layer of the first memory cell formed over the first tunnel dielectric and a second charge storage layer of the second memory cell formed over the second tunnel dielectric;
- a first control gate of the first memory cell formed over the first charge storage layer and a second control gate of the second memory cell formed over the second charge storage layer, wherein the first control gate and the second control gate are in a same row and electrically coupled via a common wordline;
- a first bitline electrically coupled to drain regions of each memory cell in the first column of memory cells,
- a second bitline electrically coupled to drain regions of each memory cell in the second column of memory cells;
- a first source line electrically coupled to source regions of each memory cell in the first column of memory cells, wherein the first source line and a source region of at least one memory cell in the first column of memory cells is electrically coupled to the first well region;
- and
- a second source line electrically coupled to source regions of each memory cell in the second column of memory cells, wherein the second source line, and a source region of at least one memory cell in the second column of memory cells is electrically coupled to the second well region.
8 more elements
A semiconductor device having a non-volatile memory (NVM) array including rows and columns of memory cells comprising:
- a well region formed within a semiconductor substrate;
- a column of memory cells, wherein each memory cell comprises:
- a source region and a drain region positioned within the well region, wherein each source region is electrically coupled to the well region;
- a tunnel dielectric layer formed over the semiconductor substrate;
- a charge storage layer formed over the tunnel dielectric layer;
- and
- a control gate formed over the charge storage layer;
- wordlines, wherein each wordline is electrically coupled to a respective control gate of a memory cell in the column of memory cells;
- and
- a bitline electrically coupled to drain regions of each memory cell in column of memory cells.
7 more elements
A semiconductor device comprising:
- a semiconductor substrate comprising a first well region and a second well region, wherein the first well region and the second well region are isolated from each other;
- a first memory cell formed in the first well region, wherein the first memory cell comprises:
- a first source and a first drain region within the first well region having a polarity different than that of the first well region;
- a first tunnel dielectric layer formed over the first source and the first drain region;
- a first charge storage layer formed over the first tunnel dielectric layer;
- and
- a first control gate formed over the first charge storage layer;
- and
- a second memory cell formed in the second well region, wherein the second memory cell comprises:
- a second source and a second drain region within the second well region having a polarity different than that of the second well region;
- a second tunnel dielectric layer formed over the second source and the second drain region;
- a second charge storage layer formed over the second tunnel dielectric layer;
- a second control gate formed over the second charge storage layer;
- and
- wherein the second memory cell and the first memory cell are electrically coupled via a wordline.
12 more elements
A method for forming a non-volatile memory (NVM) array comprising:
- forming a first well region and a second well region in a semiconductor substrate, wherein the first well region and the second well region are spaced apart by an isolation feature;
- forming a first column of memory cells positioned within the first well region;
- forming a second column of memory cells positioned within the second well region;
- forming a first tunnel dielectric of a first memory cell in the first column of memory cells and a second tunnel dielectric of a second memory cell in the second column of memory cells;
- forming a first charge storage layer of the first memory cell formed over the first tunnel dielectric and a second charge storage layer of the second memory cell formed over the second tunnel dielectric;
- forming a first control gate of the first memory cell formed over the first charge storage layer and a second control gate of the second memory cell formed over the second charge storage layer, wherein the first control gate and the second control gate are in a same row and electrically coupled via a common wordline;
- forming a first bitline, wherein the first bitline is electrically coupled to drain regions of each memory cell in the first column of memory cells;
- forming a second bitline, wherein the second bitline is electrically coupled to drain regions of each memory cell in the second column of memory cells;
- forming a first source line, wherein the first source line is electrically coupled to source regions of each memory cell in the first column of memory cells, and wherein the first source line and a source region of at least one memory cell in the first column of memory cells are electrically coupled to the first well region;
- and
- forming a second source line, wherein the second source line is electrically coupled to source regions of each memory cell in the second column of memory cells, and wherein the second source line and a source region of at least one memory cell in the second column of memory cells are electrically coupled to the second well region.
8 more elements
Dependencies are inferred from the claim text.