Method of manufacturing multi-chip stacking package
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorJen-Kuang Fang
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Abstract
The present invention discloses a method of manufacturing a multi-chip stacking package. The characteristic of the invention is that after the alignment of the bumps of at least two chips, welded bumps will be generated in a high temperature welding to form a welded bump. Furthermore, one of the at least two chips may only provide bonding pad similar to the Under Bump Metallurgy and may not provide bumps, and using the bonding pad to be welded with the bump on another chip.
Claims8
A method of manufacturing multi-chip stacking package, comprising the steps of:
- forming under bump metallurgies and bumps on a plurality of bonding pads of a first chip and a second chip;
- aligning and contacting said bumps of said first chip with corresponding bumps of said second chip;
- and
- combining said bumps of said first chip with said bumps of said second chip to form welded bumps.
A method of manufacturing multi-chip stacking package, comprising the steps of:
- forming under bump metallurgies on a plurality of bonding pads of a first chip, and forming under bump metallurgies and bumps on a plurality of bonding pads of a second chip;
- aligning and contacting said under bump metallurgies of said first chip with corresponding bumps of said second chip;
- and
- combining said under bump metallurgies of said first chip with said bumps of said second chip.
Dependencies are inferred from the claim text.