# US 2003/0102920 A1 · Ultra linear high speed operational amplifier output stage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2003/0102920 A1 - Document ID: US20030102920A1 - Status: Published application - Kind: A1 - Application number: 10/008,918 - Filed: 2001-12-03 - Published: 2003-06-05 - Earliest claimed: 2001-12-03 - Assignees: Texas Instruments Incorporated - Inventors: Neil Gibson; Marco Corsi; Tobin Hagan - Web page: https://patentgrep.com/patent/US20030102920A1 ## CPC - H03F 3/3072: {using Darlington transistors (H03F3/3074 takes precedence)} - H03F 3/26: Push-pull amplifiers; Phase-splitters therefor (duplicated single-ended push-pull arrangements or phase-splitters therefor H03F3/30) - H03F 2203/30078: A resistor being added in the pull stage of the SEPP amplifier - H03F 2203/30111: A resistor being added in the push stage of the SEPP amplifier - H03F: AMPLIFIERS ## Abstract The present invention provides an ultra linear, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage disclosed is significantly higher linearity for the same supply current, or equivalent linearity using a lower supply current. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form; δIo≈βn*βp*δIin. When used with a localized feedback circuitry, bandwidth is extended. ## Claims ### Claim 1 An operational amplifier output stage, comprising: a pre-driver sub-stage and a final sub-stage, the pre-driver sub-stage having a plurality of transistors being biased by a plurality of current sources, the pre-driver sub-stage being adapted to accept a current signal (δIin) from an input gm cell; the pre-driver stage being further adapted to provide biasing to a plurality of transistors in the final sub-stage; and the pre-driver sub-stage being coupled to the final sub-stage so as to provide current gain from input to output of δIo≈βn*βp*δIin. ### Claim 2 (depends on 1) The operational amplifier output stage recited in claim 1, further comprising localized feedback circuitry enclosed in the output stage operable to correct signal errors more rapidly than an overall amplifier feedback loop. ### Claim 3 (depends on 1) The operational amplifier output stage recited in claim 1, further comprising localized feedback circuitry and inherent RHPZ cancellation operable to extend bandwidth. ### Claim 4 (depends on 1) The operational amplifier output stage recited in claim 1, wherein the plurality of transistors in the final sub-stage comprises 4 transistors arranged as a complementary pair of differential transistors. ### Claim 5 (depends on 1) The operational amplifier output stage recited in claim 1 for use in an integrated circuit. ### Claim 6 (depends on 1) The operational amplifier output stage recited in claim 1 for use in a DSL driver. ### Claim 7 (depends on 1) The operational amplifier output stage recited in claim 1, wherein the pre-driver sub-stage comprises two circuits, the first pre-driver sub-stage circuit being adapted to condition a positive portion of an inputted signal for transfer to a first final sub-stage circuit of the final sub-stage, and the second pre-driver sub-stage circuit being adapted to condition a negative portion of an inputted signal for transfer to a second final sub-stage circuit of the final sub-stage; the first pre-driver sub-stage circuit being coupled to the first final sub-stage circuit operable to amplify the positive portion of a signal in tandem; and the second pre-driver sub-stage circuit being coupled to the second final sub-stage circuit operable to amplify the negative portion of a signal in tandem. ### Claim 8 (depends on 7) The operational amplifier output stage recited in claim 7, wherein the first final sub-stage circuit and the second final sub-stage circuit are interconnected at an output terminal node such that the conditioned and amplified positive portion of the signal and the conditioned and amplified negative portion of the signal are joined in phase with minimal crossover distortion the output signal (δIo) having the form δIo≈βn*βp*δIin. ### Claim 9 An operational amplifier output stage, comprising: a pre-driver sub-stage having a plurality of transistors configured as translinear loops such that there is minimal net signal loss or signal attenuation in the pre-driver sub-stage; a final sub-stage coupled to, and biased by currents from, the pre-driver sub-stage, operable to provide minimal cross-over distortion; and a localized feedback circuitry and inherent RHPZ in the output stage operable to extend bandwidth. ### Claim 10 An operational amplifier output stage, comprising: a first voltage supply rail Vcc connected to a first node; two connection terminals to an input stage, a first terminal connected to a second node for receiving a positive portion of an input signal and a second terminal connected to a sixth node for receiving a negative portion of an input signal; a first pre-driver sub-stage circuit coupled at the second node, the first pre-driver sub-stage circuit further comprising: a first transistor having its emitter coupled to the first voltage supply rail Vcc at the first node, and its base coupled at the second node; a second transistor having its emitter coupled to the second node and its base coupled to a third node; a third transistor having its base and collector coupled to the third node; a fourth transistor having its collector and base being coupled to a fourth node, and its emitter coupled to the first voltage supply rail Vcc at the first node; a second voltage supply rail Vee coupled to a fifth node; a second pre-driver sub-stage circuit coupled to the sixth node, the second pre-driver sub-stage circuit further comprising: a fifth transistor having its emitter coupled to the second voltage supply rail Vee at the fifth node, and its base coupled to the sixth node; a sixth transistor having its emitter coupled to the sixth node, its base coupled to a seventh node, and its collector coupled to the second node; a seventh transistor having its base and collector coupled to a seventh node; and its emitter coupled to an eighth node; an eighth transistor having its collector and base being coupled to the eighth node, and its emitter coupled to the second voltage supply rail Vee at the fifth node; a cross connection between the second transistor's collector and the sixth transistor's emitter at the sixth node, and the second transistor's emitter and the sixth transistor's collector at the second node, the cross connection resulting in a proportion of any error current flowing into the second transistor's emitter and sixth transistor's emitter to flow out through the second transistor's collector and the sixth transistor's collector into the base of the first transistor and the base of the fifth transistor; a first current source coupled between the first voltage supply rail Vcc at the first node and the second node; a second current source coupled between the first voltage supply rail Vcc at the first node and the seventh node; a third current source coupled between the second voltage supply rail Vee at the fifth node and at the third node; a fourth current source coupled between the second voltage supply rail Vee at the fifth node and the sixth node; a final sub-stage, comprising: a first final sub-stage circuit further conditioning the positive portion of the current signal provided by the first pre-driver sub-stage circuit, the first final sub-stage circuit comprising: a ninth transistor having its emitter coupled to the first transistor's collector at a ninth node, and its base and collector coupled to a tenth node; a tenth transistor having its base coupled to the ninth node, and its collector coupled to the first voltage supply Vcc rail at the first node; a second final sub-stage circuit further conditioning the negative portion of the current signal, provided by the second pre-driver sub-stage circuit, the second final sub-stage circuit comprising: an eleventh transistor having its emitter coupled to the fifth transistor's collector at an eleventh node, its base and collector coupled to the ninth transistor's base and collector at the tenth node; a twelfth transistor having its base coupled to the eleventh node, and its collector coupled to the second voltage supply rail Vee at the fifth node; a twelfth node interconnecting the tenth transistor's emitter with the twelfth transistor's emitter; and an output terminal coupled to the twelfth node. ### Claim 11 (depends on 10) The operational amplifier output stage recited in claim 10 wherein the first, second, third, fourth, ninth and twelfth transistors are pnp transistors and the fifth, sixth, seventh, eight, tenth and eleventh transistors are npn transistors. ### Claim 12 (depends on 10) The operational amplifier output stage recited in claim 10, including a localized feedback circuitry enclosed within the operational amplifier output stage. ### Claim 13 (depends on 12) The operational amplifier output stage recited in claim 12, wherein the localized feedback circuitry utilizes current feedback principles operable to substantially eliminate cross-over distortion. ### Claim 14 (depends on 12) The operational output stage recited in claim 12, wherein the localized feedback system utilizes voltage feedback principles, operable to provide unity gain. ### Claim 15 An operational amplifier output stage, comprising: a first voltage supply rail Vcc connected to a first node; two connection terminals to an input stage, a first terminal connected to a second node for receiving a positive portion of a current signal and a second terminal connected to a sixth node for receiving a negative portion of a current input signal; a first pre-driver sub-stage circuit coupled at the second node, the first pre-driver sub-stage circuit further comprising: a first transistor having its emitter coupled to the first voltage supply rail Vcc at the first node, and its base coupled at the second node; a second transistor having its emitter coupled to the second node and its base coupled to a third node; a third transistor having its base and collector coupled to the third node; a fourth transistor having its collector and base being coupled to a fourth node, and its emitter coupled to the first voltage supply rail Vcc at the first node; a second voltage supply rail Vee coupled to a fifth node; a second pre-driver sub-stage circuit coupled to the sixth node, the second pre-driver sub-stage circuit further comprising: a fifth transistor having its emitter coupled to the second voltage supply rail Vee at the fifth node, and its base coupled to the sixth node; a sixth transistor having its emitter coupled to the sixth node, its base coupled to a seventh node, and its collector coupled to the second node; a seventh transistor having its base and collector coupled to a seventh node; and its emitter coupled to an eighth node; an eighth transistor having its collector and base being coupled to the eighth node, and its emitter coupled to the second voltage supply rail Vee at the fifth node; a cross connection between the second transistor's collector and the sixth transistor's emitter at the sixth node, and the second transistor's emitter and the sixth transistor's collector at the second node, the cross connection resulting in a proportion of any error current flowing into the second transistor's emitter and sixth transistor's emitter to flow out through the second transistor's collector and the sixth transistor's collector into the base of the first transistor and the base of the fifth transistor; a first current source coupled between the first voltage supply rail Vcc at the first node and the second node; a second current source coupled between the first voltage supply rail Vcc at the first node and the seventh node; a third current source coupled between the second voltage supply rail Vee at the fifth node and at the third node; a fourth current source coupled between the second voltage supply rail Vee at the fifth node and the sixth node; a final sub-stage, comprising: a first final sub-stage circuit further conditioning the positive portion of the current signal provided by the first pre-driver sub-stage circuit, the first final sub-stage circuit comprising: a ninth transistor having its emitter coupled to the first transistor's collector at a ninth node, and its base coupled to a tenth node and its collector coupled to the second voltage supply rail Vee at the fifth node; a tenth transistor having its base coupled to the ninth node, and its collector coupled to the first voltage supply Vcc rail at the first node; a second final sub-stage circuit further conditioning the negative portion of the current signal, provided by the second pre-driver sub-stage circuit, the second final sub-stage circuit comprising: an eleventh transistor having its emitter coupled to the fifth transistor's collector at an eleventh node, its base coupled to the ninth transistor's base and collector at the tenth node and its collector coupled to the first voltage supply rail Vcc at the first node; a twelfth transistor having its base coupled to the eleventh node, and its collector coupled to the second voltage supply rail Vee at the fifth node; a twelfth node interconnecting the tenth transistor's emitter with the twelfth transistor's emitter; and an output terminal coupled to the twelfth node. ### Claim 16 (depends on 15) The operational amplifier output stage recited in claim 15, including a localized feedback circuitry enclosed within the operational amplifier output stage. ### Claim 17 (depends on 16) The operational amplifier output stage recited in claim 16, wherein the localized feedback circuitry utilizes current feedback principles. ### Claim 18 (depends on 16) The operational amplifier output stage in claim 16, wherein the localized feedback circuitry utilizes voltage feedback principles. ### Claim 19 (depends on 15) The operational amplifier output stage recited in claim 15, wherein the first, second, third, fourth, ninth and twelfth transistors are pnp transistors, and the fifth, sixth, seventh, eighth, tenth and eleventh transistors are npn transistors. ### Claim 20 A method of amplifying a signal, comprising the steps of: biasing a plurality of transistors in a pre-driver sub-stage; biasing a plurality of transistors in a final sub-stage; routing the positive cycle of the signal through a first, biased pre-driver sub-stage circuit; routing the negative cycle of the signal through a second, biased pre-driver sub-stage circuit; amplifying the positive cycle of the signal in the first, biased pre-driver sub-stage circuit; amplifying the negative cycle of the signal in the second, biased pre-driver sub-stage circuit; routing the amplified positive cycle of the signal to a first, biased final sub-stage circuit; routing the amplified negative cycle of the signal to a second, biased final sub-stage circuit; further amplifying the positive cycle of the signal in a first, biased final sub-stage circuit in tandem with the pre-driver sub-stage amplification action; further amplifying the negative cycle of the signal in a second, final sub-stage circuit in tandem with the pre-driver sub-stage amplification action; employing a plurality of translinear loops in the pre-driver sub-stage circuits and final sub-stage circuits so as to preserve the amplitude, frequency and phase characteristics of the signals during routing and amplification; and joining in phase the amplified portions of the positive and negative signal at an output stage terminal in a manner that results in high linearity and low distortion of an output signal when compared to the input signal ### Claim 21 (depends on 20) The method of amplifying a signal recited in claim 20, further comprising the step of feeding back a portion of the signal in a localized feedback system to extend bandwidth. ### Claim 22 A method of amplifying signals in an operational amplifier output stage, comprising the steps of: generating bias currents in a pre-driver sub-stage and a final sub-stage; inputting the signals into the pre-driver sub-stage and a final sub-stage; amplifying the signals in tandem in the pre-driver sub-stage and final sub-stage; employing a plurality of translinear loops in the pre-driver sub-stage and final sub-stage such that there is minimal signal loss in the pre-driver sub-stage and the final sub-stage; and using localized feedback principles so as to achieve high linearity and low distortion of an output signal when compared to the input signal.