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US 2003/0101332 A1Published application
Method of processing signed loads with the same latency as unsigned loads in a high-frequency processor
AssigneeSun Mirosystems, Inc.
InventorsDavid M. Pini, Yuefei Ge, Anup S. Tirumala
Life of this patent
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Abstract
A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.
Claims11
A method for reducing signed load latency in a microprocessor comprising:
- transferring data from a cache memory to an aligner;
- generating a sign bit for the data;
- and
- transferring the sign bit to the aligner via a bypass.
1 more element
An apparatus for reducing signed load latency in a microprocessor, comprising:
- a data path connecting a cache memory to an aligner;
- and
- a bypass connecting the cache memory to the aligner;
- wherein data is transferred from the cache memory to the aligner via the data path and a sign bit for the data is transferred from the cache memory to the aligner via the bypass.
1 more element
An apparatus comprising:
- means for transferring data from a cache memory to an aligner;
- means for generating a sign bit for the data;
- means for transferring the sign bit to the aligner via a bypass;
- means for adjusting the data during transfer to the aligner via a data path;
- means for adjusting the sign bit during transfer to the aligner via the bypass;
- means for selectively processing a part of data for use in generating the sign bit;
- and
- means for selectively processing the part of the data selected for use in generating the sign bit based on an instruction from a CPU.
5 more elements
An apparatus comprising:
- a data path connecting a cache memory to an aligner;
- a bypass connecting the cache memory to the aligner;
- wherein data is transferred from the cache memory to the aligner along the data path and a sign bit for the data is transferred from the cache memory to the aligner along the bypass;
- a select component for providing a signal to generate the sign bit for the data, wherein the select component comprises
- a sign mulitplexer;
- and a real-sign multiplexer, and wherein the select component provides a signal for choosing a part of the data to generate the sign bit for the data based on an instruction from a CPU;
- and
- wherein the aligner comprises a plurality of sub-aligners.
5 more elements
Dependencies are inferred from the claim text.