US 2003/0084271 A1Published application

Speculative execution for java hardware accelerator

AssigneeKoninklijke Philips Electronics N.V.

InventorMenno Menasshe Lindwer

Life of this patent

Estimating the term…

Loading patent…

Abstract

Conditional branch bytecodes are processed by a Virtual Machine Interpreter (VMI) hardware accelerator that utilizes a branch prediction scheme to determine whether to speculatively process bytecodes while waiting for the CPU to return a condition control variable. In one branch prediction scheme, the VMI assumes the branch condition will be fulfilled if a conditional branch bytecode calls for a backward jump and that the branch condition will not be fulfilled if a conditional branch bytecode calls for a forward jump. In another branch prediction scheme the VMI makes an assumption only if a conditional branch bytecode calls for a backward jump. In yet another speculative execution scheme, the VMI assumes that the branch condition will be fulfilled whenever it processes a conditional branch bytecode. The VMI only speculatively processes bytecodes that are easily reversible, (for example, bytecodes representing simple stack manipulations), and suspends speculative processing of bytecodes upon encountering a bytecode that is not easily reversible. The assumptions made by the VMI are confirmed or invalidated upon receipt of the condition control variable. If an assumption is invalidated, any speculatively processed bytecodes are reversed.

Claims18

Dependent claims

A method of processing virtual machine instructions, the method comprising the steps of:

identifying a subset of virtual machine instructions the processing of which is conditionally dependent upon the value of a condition control variable;
fetching and processing a range of the virtual machine instructions into native instructions executable by a processor, wherein a virtual machine instruction counter is incremented after processing and dispatching to the processor for execution a virtual machine instruction of said range, and continuing until a member of said subset of the virtual machine instructions is encountered;
initiating a control value retrieval process upon encountering said member, by dispatching native instructions represented by said member to the processor for execution;
and
processing a speculative sequence of virtual machine instructions when an assumption has been made for an assumed value of a real value of the condition control variable, by:
switching a speculative mode switch on;
updating the virtual machine instruction counter according to the assumed value, so as to process into native instruction each virtual machine instruction of said speculative sequence of virtual machine instructions, incrementing the virtual machine instruction counter and dispatching the native instructions after each virtual machine instruction is processed, until the real value of the condition control variable has been received;
comparing the real value to the assumed value;
and
reversing the processing of the speculative sequence of virtual machine instructions, purging a speculation mode history, and reversing the update to the virtual machine counter, if the real value is not equal to the assumed value;
or
switching said speculation mode switch off and purging said speculation mode history, if the real value is equal to the assumed value;
delaying further fetching and processing of the range of the virtual machine instructions until the real value of the condition control variable is received and then processing the next virtual machine instruction according to the real control value, if no assumption is made for the assumed value of the real value of the condition control variable.

10 more elements

A method of processing virtual machine instructions, the method comprising:

fetching and processing a range of the virtual machine instructions into native instructions executable by a processor, and continuing until a conditional branch instruction is encountered;
initiating a control value retrieval process by dispatching a native instruction represented by the conditional branch instruction to the processor for execution, upon encountering the conditional branch instruction;
determining whether to make an assumption as to a value of a condition control variable;
and
processing a speculative sequence of virtual machine instructions when an assumption is made as to the value of the condition control variable, by:
processing a virtual machine instruction of said speculative sequence of virtual machine instructions into a preliminary native instruction, only if the virtual machine instruction is easily reversible;
and
suspending processing of said speculative sequence of virtual machine instructions until the value of the condition control variable is received, if the virtual machine instruction does not represent a stack manipulation,
delaying further fetching and processing of the range of the virtual machine instructions until the value of the condition control variable is received and then processing the next virtual machine instruction according to the received value, if no assumption is made as to the value of the condition control variable.

6 more elements

An apparatus for processing virtual machine instructions, comprising:

a processor (110) having a native instruction set and configured to execute native instructions;
an instruction memory (150), configured to store virtual machine instructions;
a preprocessor (120), configured to fetch virtual machine instructions from the instruction memory and to process the fetched virtual machine instructions into native instructions executable by the processor (110), to identify conditional virtual machine instructions, to determine whether to speculatively process virtual machine instructions while the value of a condition control variable is being sent by the processor, and to confirm or reverse said speculatively processed virtual machine instructions upon receipt of the condition control variable, and further comprising:
a control register (180), configured to store the value of the condition control variable received from the processor;
a virtual machine instruction counter, configured to indicate the next virtual machine instruction to be processed;
an assumption variable register, configured to store the value of an assumed control variable;
a speculation mode bit, configured to indicate whether the preprocessor has made an assumption regarding the value of the condition control variable;
and
a speculation mode history, configured to store speculation mode bits while the value of the control variable is being sent.

6 more elements

Dependencies are inferred from the claim text.