Method and apparatus for a multi-purpose domino adder

A computer readable storage medium including program instructions that direct a computer to function in a specified manner when executed by a processor, the program instructions comprising:

• calculating, via a static initial sum adder, an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal;
• concurrent with calculating initial sums, generating, via domino initial carry-out logic, an initial carry-out signal for each initial sum previously calculated by the static initial sum adder;
• calculating, via a static intermediate sum adder, an intermediate sum for each group of M-initial sums according to a respective initial carry-out value of each initial sum calculated by the static initial sum adder;
• concurrent with calculating intermediate sums, generating, via domino intermediate carry-out logic, an intermediate carry-out signal for each intermediate sum generated by the static intermediate sum adder;
• and
• calculating a final sum value from the calculated intermediate sums according to a respective intermediate carry-out of each intermediate sum previously calculated by the static intermediate sum adder.

An adder, comprising:

• a processor having circuitry to execute instructions;
• an input selection device coupled to the processor, the input selection device to receive a plurality of corresponding addend and augend signal;
• a domino carry propagation/generation circuit to generate one of carry propagation signals, carry generation signals, group carry generation signals and group carry propagation signals, according to received domino augend signal and a received domino addend signal;
• a static half sum adder to generate half-add sums of each corresponding N-bit portions of the received augend signals and the received addend signals;
• and
• a storage device coupled to the processor, having sequences of instructions stored therein, which when executed by the processor, cause the processor to:
• calculate an initial sum for each N-bit portion half-add sum utilizing corresponding carry generation and carry propagation signals,
• concurrent with calculation of initial sums, generate a carry-out signal for each calculated initial sum utilizing corresponding group carry propagation signals and group carry generation signals,
• select an intermediate sum for each group of M-initial sums according to a respective carry-out value of each previously calculated initial sum,
• concurrent with selection of intermediate sums, generate an intermediate carry-out for each generated intermediate sum, and
• select a final sum value from the calculated intermediate sums according to a respective carry-out of each previously generated intermediate sum.

An electronic system comprising:

• a printed wiring board on which a parallel bus is formed, an integrated circuit (IC) chip package being operatively installed on the board to communicate using the parallel bus, the package having an IC chip that includes a logic function section and an I/O section as an interface between the logic function section and the bus, the logic function section includes a domino adder in which a static sum calculation path includes initial sum calculation logic, intermediate sum selection logic and final sum selection logic and a domino carry-chain generation path that includes carry propagate/generate logic, initial carry generation logic and intermediate carry generation logic;
• and
• wherein, the initial sum calculation block receives static input addend and augend signals, while the carry propagate/generate logic receives domino addend and augend signals to generate group propagate/generate terms and an initial carry-in for the sum calculation block to generate initial N-bit sums provided to the intermediate sum selection block to select groups of M-initial sums to form intermediate sums in response to initial carry-in signals generated by the initial carry generation logic in response to the group propagate/generate terms, the final sum selection logic to select received intermediate sums, in response to intermediate carry-in signals generated by the intermediate carry generation logic in response to the group propagate/generate terms, to form a final sum of the received addend and augend signals assuming a carry-in equal to one and a carry-in equal to zero.